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I am trying to check the condition of an output (which can be set later in the code) but it does not seem like you can do this.

How do you check the condition of an output signal within an if statement?

entity turbine_action is
Port (  freq550 : in STD_LOGIC;
        freq650 : in STD_LOGIC;
        freq850 : in STD_LOGIC;
        freq950 : in STD_LOGIC;
        user_ip : in STD_LOGIC;
        mild : out STD_LOGIC;
        aggressive : out STD_LOGIC;
        brake : out STD_LOGIC;
        alarm : out STD_LOGIC;
        clock : in STD_LOGIC);
end turbine_action;

architecture Behavioral of turbine_action is

type state_type is (s0, s1, s2);
signal current_s, next_s : state_type;

begin

process (clock)
begin
    if (rising_edge(clock)) then
        current_s <= next_s;    --change state according to next state logic
    end if;
end process;


process (current_s, freq550, freq650, freq850, freq950, user_ip)
begin
    case current_s is
        when s0 =>
        if (user_ip = '1') then
            if (freq550 = '1') then
                brake <= '1';
                alarm <= '1';
                -- ADD DELAY delay(1000);
            end if;
            if (freq650 = '1') then
                if (mild = '1') then
                    aggressive <= '1';
                end if;
            end if;

end Behavioral;
MRB
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  • Reading an output is not allowed in early version of VHDL compilers. The solution is to make a local signal which you use everywhere. You can also read that. Then in one place assign the local signal to your output. Or you can see if you have access to a newer VHDL compiler. For reason too complex to explain in a comment do **not** make the output a `buf` type. Theoretical it is possible. Practically, anybody with experience has learned **not** to do that. – Oldfart Nov 02 '19 at 17:34
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    A [mcve] includes a complete example reproducing a particular error. This is missing a complete case statement, if statement and process which the error falls within in the question as well as a context clause. The question is a duplicate (search terms *[vhdl] "cannot read output"*), e.g. [VHDL - Phase Accumulator with feedback](https://stackoverflow.com/questions/54541371) with a shown solution. Oldfart's *mode* `buffer` lacks wide synthesis vendor tool support historically while in -2008 *mode* `out` provides the same semantics as mode `buffer` - `mild` can be evaluated. –  Nov 02 '19 at 18:31
  • Does this answer your question? [VHDL - Phase Accumulator with feedback](https://stackoverflow.com/questions/54541371/vhdl-phase-accumulator-with-feedback) – mkrieger1 Nov 10 '19 at 19:37

1 Answers1

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Let say you will use this:

alarm : out STD_LOGIC;

You can define it as inout signal:

alarm : inout STD_LOGIC;

Or you can connect it with an signal (assuming you defined a std_logic signal): 

local_signal <= alarm;

Then you can check the condition of local_signal.

Normally output vectors are going to one top vhd file and they can be controlled at that vhd file due to they came as input vector.

inspiron
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