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I'm new to EDA and I have the following verilog code and i need to identify the synchronous reset clearly.

module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk)
  begin
    if(rst)
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule

is 'rst' a reset (synchonous) ?

yasara malshan
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    What do you mean by 'identify'? `rst` is (a) a reset and (b) synchronous. – Matthew Taylor Oct 24 '19 at 12:02
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    synchronous in this case means that the reset is fully synchronized with the clock. In your case the reset can happen at the posedge of the clock only. So, it is synchronous. – Serge Oct 24 '19 at 13:03
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    there is no signal 'b' in your example. All this is a matter of interpretation by synthesis tools. Read about synthesizable subset of verilog. The behavioral coding style in your example maps to the behavior of a synchronous reset flop in hardware. Synthesis tools just recognize the behavioral style. – Serge Oct 24 '19 at 13:28
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    *"I need to identify"* Is this a school assignment? – Oldfart Oct 24 '19 at 13:50
  • sorry @Serge, it is 'rst' – yasara malshan Oct 24 '19 at 14:56

2 Answers2

4

The accepted answer is wrong, since the 2nd code sample is actually a Combinational code and doesn't use clock at all, we need to implement a Sequential code. The first code sample is a Synchronous Reset:

//Synchronous Reset
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk) 
  begin
    if(rst) // In order to execute this line, clk and reset both have to be in posedge.  
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule

The second code sample is an Asynchronous Reset:

//Asynchronous Reset
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk, posedge rst) 
  begin    
    if(rst) // In order to execute this line, rst has to be in posedge(clk's value doesn't
            // matter here, it can be either posedge or negedge, what's important is rst's value). 
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule
Null3rror
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1

Below is your code with synchronous and asynchronous resets.

//Synchronous Reset
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @(posedge clk) //This clock makes the reset synchronized to a clock signal.
  begin
    if(rst)
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule

//Asynchronous
module test(clk,d,rst,a);
  input clk,d,rst;
  output reg a;

  always @* //No clock to synchronize with. 
  begin     //Reset signal will drive anytime a input value changes
    if(rst)
      a <= 1'b0;
    else
      a <= 1'b1; // assigned to a constant
  end
endmodule
Laburtz
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