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I need some clarity on how a direct mapped cache in MIPS works for an array. For example, for an array of ten items a[0] to a[9], and the following direct mapped cache configuration: Direct mapped cache with total cache size of 32 bytes and block size of 16 bytes. Each memory address is 32 bits.

Which would yield: 4 bits offset, 1 bit index, 27 bits tag

My cache would look like this:

| Index | Valid | Tag | W0 | W1 | W2 | W3 |
|   0   |   0   |     |    |    |    |    |
|   1   |   0   |     |    |    |    |    |

My question is, on my first load for a[0], I understand that in each cache index, we can store 4 words. Does this mean a[0], a[1], a[2], a[3] all gets loaded into the cache on load access for a[0]? So a[1], a[2], and a[3] will be a hit.

Or am I understanding it wrongly?

Simson
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Iva
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1 Answers1

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It depends on the alignment of a[0].

Let's assume a[0] is at 0x10010000.  Then the block of 16 bytes that is loaded starts at 0x10010000 and goes thru 0x1001000F.

a[0] is at 0x10010000, a[1] is at 0x10010004, a[2] is at 0x10010008, and a[3] is at 0x1001000C — all in that cache line.

However, if a[0] is at 0x10010004, then the block of 16-bytes that is loaded is still the same block at 0x10010000, but now contains the word in front of a[0], a[0], a[1], and a[2], but not a[3].

However, if a[0] is at 0x10010008, then the block of 16-bytes that is loaded is still the same block at 0x10010000, but now contains the two words in front of a[0], a[0], a[1], but not a[2] and not a[3].

We're also assuming that the elements of a are 4 byte integers.  MIPS has an alignment requirement for integers but that is only 4 bytes, not 16 bytes.  So, there is no reason to presume that a is anything more than 4 byte aligned, unless we are told something more.

Erik Eidt
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  • Thank you! Yes, I guess the alignment matters a lot, and in this case they map out nicely (starts at 0000). Can I also quickly check that my calculations for my tag, index and offset are right? I sometimes find it hard to calculate these, because during my lecture I was given more information to derive those, but in my tutorial, they only gave me the 'total size of cache' and 'block size' (which I assume is the cache size?) – Iva Oct 16 '19 at 00:32
  • Yes, you are correct. A direct mapped cache is the same as a one-way set associative cache. So, we divide the total cache bytes (32) by 1 = 32, ((for 2-way we would divide by 2 here instead)), and then since the block size is 16 we determine there are only two index positions (0,1 = 1 bit) of 16 bytes in 32 bytes. – Erik Eidt Oct 16 '19 at 00:35