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In logic design convention, a clock input port is designated by an embedded triangle while an active low port has a bubble as shown in this d-flip-flop example.

Now the bubbled I/O's I can do (if somewhat counter-intuitively) using arrowhead and arrowtail. But I can't see how to make an arrowhead extend just into the port. Ideally, this would be a characteristic of the port rather than the connecting arrow but that is a lesser concern.

albert
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Eric Edwards
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  • You may do this in a way similar to this: https://stackoverflow.com/questions/58066677/in-graphviz-how-do-i-add-a-shape-in-the-middle-of-an-edge/58094960#58094960 – Dany Oct 11 '19 at 05:38

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