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I'm practicing converting a Mips instruction (beq $t5, $s0, loop) to binary based on the Mips reference sheet and there are a series of instructions (PC=PC + 4 + branch address) for computing the immediate value for an "I" type instruction and it keeps referencing "PC."

What does PC refer to? It seems like I'm supposed to be looking for where the "loop" label is stored in memory-: specifically finding that memory address.

Peter Cordes
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kocho84
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    **P**rogram **C**ounter, i.e. the address of the current instruction. See _MIPS32™ Architecture For Programmers Volume I: Introduction to the MIPS32™ Architecture_, section 2.8.4.2. – Michael Oct 06 '19 at 10:46

1 Answers1

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Intel architectures call this the Instruction Pointer, instead of Program Counter.  Either name refers to the same thing: a register that identifies the address of the current/next instruction for the processor to execute.

Oversimplifying a bit (i.e.assuming s non pipelined processor) at the beginning of a clock cycle, the PC holds the address of the instruction that will execute during the clock cycle, aka the current instruction.  By the end of the clock cycle, the PC register is updated to hold the address of the instruction that will execute in the next clock cycle.

PC = PC + 4 describes sequential execution as used by, say, add, addi, and by not-taken conditional branches: it says that the next PC will refer to the instruction 4 bytes beyond the current one — that for (normal) sequential flow, the PC steps forward 4 bytes at a time.

The expression PC = PC + 4 + branch address is somewhat of a misnomer — it should say PC = PC + 4 + offset where offset is the immediate in the I-Type instruction, more specifically the signed (sign extended from 16-bits to 32-bits) immediate * 4.

In this formula, the PC on the right hand side of the = refers to the current instruction: the address of the beq instruction, while the PC on the left hand side refers to the next PC to execute after the beq.   This formula describes the instruction address to execute next when the branch is taken, as this is a conditional branch (if the branch is not taken then PC = PC + 4 describes sequential execution).

For conditional branches, a value for the immediate of -1 will branch to self, 0 will branch to the next instruction, and 1 will skip one instruction ahead.

Erik Eidt
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    There can be confusion between PC (the register) vs. the address of the instruction being executed. As in many ISAs, MIPS branches are relative to the *next* instruction as you say. Documenting this as `target = PC + 4 + offset` implies that PC holds the address of the current instruction. But then you have diagrams like in [How to Calculate Jump Target Address and Branch Target Address?](//stackoverflow.com/q/6950230) that show more likely hardware where a physical register holds the next fetch address *after* the one being decoded. But the text of that answer says PC+4 :/ – Peter Cordes Oct 06 '19 at 17:14
  • In my experience, the PC is the address of the next CPU instruction. – Russell Hankins Dec 07 '22 at 15:41