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I'm trying to write some Data to a Dual Port BRAM and read it from PL. I created a customised BRAM from the IP Catalog and put it in a wrapper so i can use it in the Block diagram. PORTA width is 32-bit and PORTB width is 256-bit. I need to transfer 1024 8-bit values, so PORTA depth is 256 (8bit) and PORTB depth is 32 (5bit). I use the standard BRAM-Controller in 32-bit mode (depth is 2048, but this shouldn't matter?).

Block Diagram

To write Data to the BRAM over the AXI-Interface i use the function Xil_Out32(BASE_ADDR+0, 0xFFFFFFFF). When i want to access the next 32-bit of data in the BRAM is use Xil_Out32(BASE_ADDR+4, 0xFFFFFFFF). +4 cause the memory is byte aligned, right? (When i use +1 my program crashes).

To read Data from the BRAM over PL i simply put a Address on addrb[4:0] and get my data two clock cycles later out of doutb[255:0]. Cause "addrb" is only 5 bit, this can't be byte aligned, so every time i add +1 to addrb i get the next 256-bit from BRAM, right?.

OK. Now to my problem: I execute the following on PS:

Xil_Out32(BASE_ADDR+0, 0xFFFFFFFF);
Xil_Out32(BASE_ADDR+4, 0xAAAAAAAA);

and read address 0x00 on my 256-bit output from PL the output looks like this:

0x000000000000000000000000AAAAAAAA000000000000000000000000FFFFFFFF

I also put this in a little Diagram, to make it more clear:

Problem Description

I hope someone can put me in the right direction ...

Alexey Usharovski
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delviewtravian
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  • I did some further research and started Simulating my Problem on the PL Side. I Write the following Data into BRAM: addra: 0x00 Data: 0xAAAAAAAA addra: 0x01 Data: 0xBBBBBBBB addra: 0x02 Data: 0xCCCCCCCC ... addra: 0x08 Data: 0x11111111 Now my 256-bit output reads: addrb: 0x00 Data: 0x.....CCCCCCCCBBBBBBBBAAAAAAAA addrb: 0x01 Data: 0x...........................................11111111 So everything is as I expect. This leaves me with the Problem how I access Address 0x01, 0x02, 0x03 from PS side with AXI ??? My program just crahes when I access address different from n*0x04 – delviewtravian Sep 27 '19 at 13:58
  • Here is my solution to this problem: I created a vhdl module which shifts the input right by two bits (divide / 4) and put it between the address output from the bram controller and the bram itself. Now i can access the whole BRAM from the PS in 0x04 increments – delviewtravian Oct 07 '19 at 15:26

1 Answers1

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Cause "addrb" is only 5 bit, this can't be byte aligned, so every time i add +1 to addrb i get the next 256-bit from bram, right?.

That conclusion is a bit too fast. It greatly depends how all your address buses are connected. Standard the AXI address bus always has the LS address bits even if they are never used.

For example my a AXI DMA engine has a 128 wide data bus. The address port still has:

output logic  [31:0] m_axi_awaddr,

However the bottom 4 address bits [3:0] are always zero. I MUST increment my address bus in steps of 16 (16 bytes is 128 bits) if I want to write consecutive locations in memory.

But elsewhere I have an VGA adapter with 8bits wide 4K deep BRAM where I connect AXI[2] to BRAM A[0]. Now I have to increment my address bus in steps of 4 if I want to write consecutive byte locations in BRAM memory.

Oldfart
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  • addrb is being driven by PL. It is 5 bits wide, so the maximum avaibable options are 32. But my memory is 256bit*32. So I don't see another way ... I already tried adding +1 on PL side and this seems just fine. If I do: Xil_Out32(BASE_ADDR+0, 0xFFFFFFFF) Xil_Out32(BASE_ADDR+4, 0xAAAAAAAA) Xil_Out32(BASE_ADDR+8, 0xBBBBBBBB) Xil_Out32(BASE_ADDR+16, 0xCCCCCCCC) I get addrb 0x00: 0x000000000000000000000000AAAAAAAA000000000000000000000000FFFFFFFF 0x01: 0x000000000000000000000000CCCCCCCC000000000000000000000000BBBBBBBB I think you are reffering to AXI addressing, which i can rep – delviewtravian Sep 27 '19 at 10:16
  • reproduce ... On the 32-bit Input side of my bram I have to do +4 to get to the next 32-bit (AXI-Addressing) – delviewtravian Sep 27 '19 at 10:19