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I am working on some research project based on ZC706 board that contain Zynq-7000 soc. i need to know that Cortex-A9 Cpu in Zynq-7000 implemented Return Stack Buffer (Return Stack Buffer is an program flow speculation technique like branch prediction) or no. In Zynq-7000 Technical reference manual i saw some registers that indicate that Return Stack was implemented or no.

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as you can see in ETMCCER register bit 23 indicate return stack implementation detail and it's reset value is 0.

now i want to know that this means that Return Stack did not implemented in this SOC? Right?

excuse me for simple question, but i am really in doubt and i am wondering that implementing of return stack buffer is optional in ARM cores.

alireza sadeghpour
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    Many SOC features are options. Consider a Cortex-A9 with 128kB or 4MB of L2 cache; they will complete the same code at different times. The RSB is an optimization to avoid memory loads and keep a pipeline full. The same binary code will produce the same results, with a different timing. What a vendor populate for CORE memory (DDR) will also affect timing. Some DDR is faster than others and may have more wait states/delay if no cache has the data. So, the return stack is optional, just like the documentation states. – artless noise Sep 22 '19 at 13:36

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The return stack feature in the PTM is unrelated to performance features in the processor.

With PTM (and ETMv4), an indirect branch address does not need to be traced if it matches the state of a previously traced branch and link instruction. This allows some reduction in the trace bandwidth.

All PTM and ETM built for A-class CPU will probably implement the return stack. Since all these registers above are RAZ, I'm guessing there is no PTM in this device (but that contradicts the datasheet).

Sean Houlihane
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