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I am reading the DVCON paper 2006 "Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertings" by Mark Litterick. I am confused with some of the statements

  1. Page 2 Section 4.2 Input data values must be stable for three destination clock edges.

the paper seems to imply positive edges since that is what the property p_stability seems to check. But the paper by Clifford Cummings (CDC design and verification techniques Using System Verilog) mentions this as 1.5x. So he is suggesting 2 positive and 1 negative edge. Can someone confirm if the paper meant positive edge?

  1. Page 5, Section 6, Figure 11 Synchronizer will Jitter Emulation allows 3 clock delay randomly. For a single-bit input, how do we get 3 clock delay? I can see that being useful for multi-bit input where there is some skew but not for a single bit. 
property p_stability;
@(posedge clk)            // NOTE POSITIVE EDGE
    !$stable(d_in) |=> $stable(d_in)[*2];
endproperty
Sanjeev Singh
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2 Answers2

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I can confirm the intent of the original statement is 3 positive edges, let me explain why. It is quite straightforward to identify the potential for a pulse that is two positive edges wide to be filtered - specifically if the actual pulse (lets say high level) violates the setup time for the first edge and the hold time for the second edge, then RTL simulation would see the signal as high for two clock edges, but it could be filtered out completely due to metastability. If the verification remains in the event driven simulation domain, then a safe verification margin is to say we can (only) guarantee propagation if it is observed for 3 consecutive positive edges.

Now the reality, in the time domain rather than event driven domain, is that the pulse width must be strictly greater than the clock period plus the setup and hold times.... which is more than two edges but less than three. But you would need a temporal check to validate that, not an event based check.

(for the second question, I need to go back to the paper myself)

Hope that helps, Mark

Mark Litterick
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  • Thanks, Mark, That makes sense. Just to recap, the min requirement would be clock period + setup+hold but for ease of temporal checking it is safe to make it 3 +ve edges. – Sanjeev Singh Sep 11 '19 at 14:20
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I read both papers a while back. My understanding is Clifford Cummings's statement is more accurate. D input width > 1.5x receiving clock period is the minimum requirement. This will guarantee to have 2 positive sampling edges and some space for hold and setup time.

Shaun Feng
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