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I am trying to model a simple direct mapped cache with main memory module which is an sc_cthread and a main memory state machine which also an SC_CTHREAD. I am observing one clock cycle delay from writing to a signal from my main memory module and receiving it on state machine.

How can I do it in only one clock cycle?

cccnrc
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Dan
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1 Answers1

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You cannot avoid the latency between threads when using an SC_CTHREAD. When writing to an sc_signal from one CTHREAD, the value change will only be visible to another CTHREAD at the next clock edge.

If you must use a CTHREAD (i.e. using high-level synthesis), then the only way to avoid the cross-thread latency is to place both functionalities within a single CTHREAD.

If you only need a behavioral model for simulation, then you could use SC_THREADs and sc_events. One thread can generate an sc_event that is being waited on by the second thread. When the second thread wakes on that event, it can observe sc_signal changes done by the first thread, and then produce an output (aligned with the clock edge if desired). Using sc_events gives the opportunity to sample and update signals "between" clock edges.

Mr Bone
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    thank you very much for your reply. Please also can you tell me how can I model a register in SC_THREAD. Since I know that if a variable is declared an sc_signal in SC_CTHREAD than it behaves like a register but how can I do that in SC_THREAD. I can make SC_THREAD sensitive to clk.pos() and reset but I do not think that it will model the registers where I want. – Dan Aug 13 '19 at 14:21
  • Making the sc_thread sensitive to clk.pos() and reset is enough to make the sc_signal functionally a register. – Mr Bone Aug 13 '19 at 19:01