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I understand the difference between packed and unpacked arrays in SystemVerilog (7.4 of the LRM).

I have a two dimensional array that I can code with one of the dimensions as either packed or unpacked.

Intuitively I would try to code that dimension as unpacked as it seems neater, but I wonder if there is actually any synthesis difference between the two.

WestHamster
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2 Answers2

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The difference mainly depends on the operations you perform on the array. There is overlap in the functionally allowed with packed and unpacked arrays. Choosing one over the other limits certain kinds of operations. But in general, packed arrays let you access all the elements at once so you can perform arithmetic or logical operations across all the bits. That might affect how well a synthesis tool will optimize the array (same for simulation performance).

dave_59
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For synthesis, everything will be flattened. All hierarchies, array (packed, unpacked) everything will be flattened and only single file will be generated.

Here is an example -

Packed & Unpacked net in RTL - 

logic [15:0] next_image_r_p2 [3:0][3:0];         // Pipeline Stage - 2

After Synthesis (For next_image_r_p2[3][3] net and similar for others) - 

wire     next_image_r_p2_3__3__10_, next_image_r_p2_3__3__9_,
         next_image_r_p2_3__3__8_, next_image_r_p2_3__3_7_,
         next_image_r_p2_3__3__6_, next_image_r_p2_3__3__5_,
         next_image_r_p2_3__3__4_;

So basically either packed or unpacked, tool will consider it as a single net only (in this case 4*4*16 = 256 nets).

Karan Shah
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