How to pass a string variable (not a string literal) to $dumpfile system task?

Question

I am running simulations with different parameters passed to the testbench as plusargs. I want to dump a separate VCD file for each of these runs. I tried declaring a string variable and constructing the file name using the parameters passed, and pass this on to $dumpfile.

    string file_name;
    file_name = "tx_dsp.vcd"
    $dumpfile(file_name);

But, I am getting the following error in IES:

Passing string variable to this system task/function is currently not supported

As a workaround, I defined the file name from the command line and used it as argument to $dumpfile. This works, but not if the test parameters were randomized from inside the testbench.

Is this the behaviour of simulator or SystemVerilog?

Answer 1

According to the SystemVerilog LRM, it should be possible. In 21.7.1.1, it says the following:

dumpfile_task ::=
$dumpfile ( filename ) ;

The filename is an expression that is a string literal, string data type, or an integral data type containing a character string that names the file to be opened. The filename is optional and defaults to the string literal "dump.vcd" if not specified.

You are using a string data type in your example (Section 6.16 in the aforementioned document). An advantage is that the length of the string is dynamic and that no truncation can occur.

String literals (Section 5.9 in the LRM), on the other hand, behave like packed arrays. If your compiler does not support string data types in $dumpvars, you can try to define file_name as a string literal:

reg[N*8:0] file_name;
file_name = "tx_dsp.vcd"
$dumpfile(file_name);

Here, Nis the maximum number of characters in your string.

Please also take a look at Section 11.10 in the LRM. This section describes operations on string literals.