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I tried AMD’s website, wikichip, wikipedia, google, several review websites and for the love of god and everything that is holy they ALL omit L1 cache size but mention L2 and L3. So please, if you own one these new processors, could you run “lscpu” and “/proc/cpuinfo” and post the results? Thank you.

Peter Cordes
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1 Answers1

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https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 says L1I size is 32kiB / 8-way, down from 64kiB / 4-way in Zen/Zen+. Presumably L1d stays the same, at 32kiB. https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/ quotes some AMD slides that confirm L1I size.

Staying with 32kiB / 8-way for L1d is extremely likely; that's the sweet-spot for VIPT caches with 4k page size so it's certainly your go-to organization to avoid any aliasing problems.

If L1d cache size had changed, that would have been mentioned in the same articles that detail these other changes.

The "Zen 2 cache hierarchy" slide on https://hexus.net/tech/news/cpu/131549-the-architecture-behind-amds-zen-2-ryzen-3000-cpus/ also confirms 32kiB each L1d + L1i explicitly showing 32kiB / 8-way L1d.

This was on the first page of google results for zen 2 l1d cache size

Peter Cordes
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    Sunny Cove has a 48KiB data cache (increased from 32KiB in Skylake and Palm Cove). This is achieved by adding 4 more cache ways, so the virtual cache set index is still equal to the physical index. – Hadi Brais Jul 15 '19 at 07:15
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    @HadiBrais: yeah, I was reminded of that while searching re: Zen2. First time Intel's done anything but 32k / 8-way for either of the L1 caches for a long time. That dates back to at least Merom / Core 2 over 10 years ago. AMD has played around with larger / less-associative L1i caches various times, and in Bulldozer family smaller write-through L1d caches + an even smaller write-combining buffer. – Peter Cordes Jul 15 '19 at 07:19