0

I have a board I'm working on with a Zynq 7020 chip on board, along with DDR memory (and other components which don't matter much to this question). For information, I've configured the memory controller to enable ECC, so I have 125 MB of effective RAM on the DDR chips.

I need to be able to read the entire RAM via JTAG, but am having difficulties understand what addresses to read and which read command to use.

I'm looking at the memory map (in the Zynq 7000-series technical reference manual), and am currently using xmd for the debug interface after connect arm hw.

System Addresses Memory Map from the Technical Manual

Firstly, there are several things with notes. My understanding, though it's not stated explicitly anywhere, is that this means "0x0 is mapped to the OCM if it's not filtered by the SCU and the OCM is mapped low, but it goes to DDR if it's filtered by the OCM".

If your address is filtered by the SCU, then does this mean that 0x0 to 0x0 + DDREffectiveSize is mapped to DDR, but only the addresses starting at 0x8_0000 of RAM are accessibly to non-CPU/ACP devices? Or does the RAM actually start at 0x8_0000 and everything below that maps to nothing?

xmd has multiple commands to read memory: mrd and mrd_phys. The documentation on the latter says "Cortex A9 Memory Read through AHB AP" and, if you use -force, "Read from OCM at 0x0 (iff DDR is not remapped to 0x0)". However, it's not clear (to me) whether either of these gets mapped by the SCU or not, or if they turn into direct AXI transactions. Ideally (for other things I want to read too), I'd like to my reads to turn into AXI transactions, but that may not be reasonable.

How can I tell whether either of these commands goes through the SCU and how can I tell exactly where the various components are mapped?

iAdjunct
  • 2,739
  • 1
  • 18
  • 27
  • @artless_noise The system is currently running with software that’s communicating correctly over the network, so the PS is already set up correctly (thanks in large part to Xilinx magic creating the ps7_init stuff). The board is running when I connect the JTAG. – iAdjunct Jul 11 '19 at 17:35
  • Is this software in ddr? Ddr also needs power, that is correct. The ddr controller is possibly in the iOS space. – artless noise Jul 11 '19 at 17:36
  • I don’t know for sure, but my system is a VxWorks system with a 21MB elf file, and that definitely wouldn’t fit on the SRAM so I suspect so – iAdjunct Jul 11 '19 at 17:38
  • Scu filtering just means you can see l2 cache if the ddr is dirty. The address range seems to only apply to a 256k sram which can be aliased via this chart. – artless noise Jul 11 '19 at 17:41
  • The 1m to 64mb range is ddr no matter what. Alias means multiple bus addresses go to the same ddr cell. – artless noise Jul 11 '19 at 17:49
  • How do I know what’s aliased? I haven’t seen *any* reference to aliasing addresses. – iAdjunct Jul 11 '19 at 17:58
  • It often depends on ddr controller setup and ddr size. I assume 1Mb (0x100000) is the best place to access from the chart. – artless noise Jul 11 '19 at 18:00

0 Answers0