how can i convert entity of bloch which takes 4 inputs to 2 inputs?
http://dl.dropbox.com/u/2879760/sample.PNG
A you see here i use three the same mux :( how to take in etykieta2 only two inputs?
code:
library ieee;
use ieee.std_logic_1164.all;
library work; --domyslnie zawieta moj pakiet
use work.mux_package.all;
entity glowny is
generic(
n : integer := 4;
k : integer := 2
);
port(
a, b, c, d,e,f,g,h : in std_logic_vector(n-1 downto 0);
s : in std_logic_vector(1 downto 0);
t : in std_logic_vector (1 downto 0);
y, x, z : out std_logic_vector(n-1 downto 0)
);
end glowny;
architecture multiplekser of glowny is
signal xx,yy,zz : std_logic_vector(n-1 downto 0);
for etykieta: mux use entity work.mux(arch_mux5);
for etykieta1: mux use entity work.mux(arch_mux6);
for etykieta2: mux use entity work.mux(arch_mux3);
begin
etykieta:
mux generic map (n=>n) port map (a=> a, b=>b, c=>c, d=>d,s=>s, y=>xx);
etykieta1:
mux generic map (n=>n) port map (a=> e, b=>f, c=>g, d=>h,s=>s,y=>yy);
etykieta2:
mux generic map (n=>n) port map (a=> yy , b=>yy, c=> xx, d=>xx, s=>t ,y=>zz);
end multiplekser;
packages
library ieee;
use ieee.std_logic_1164.all;
entity mux is
generic(
n : integer := 4
);
port(
a, b, c, d : in std_logic_vector(n-1 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(n-1 downto 0)
);
end mux;
-- przypisanie podstawowe - concurrent signal assigment
architecture arch_mux1 of mux is
begin
y(0) <= (a(0) and not(s(1)) and not(s(0)))
or (b(0) and not(s(1)) and s(0))
or (c(0) and s(1) and not(s(0)))
or (d(0) and s(1) and s(0));
y(1) <= (a(1) and not(s(1)) and not(s(0)))
or (b(1) and not(s(1)) and s(0))
or (c(1) and s(1) and not(s(0)))
or (d(1) and s(1) and s(0));
y(2) <= (a(2) and not(s(1)) and not(s(0)))
or (b(2) and not(s(1)) and s(0))
or (c(2) and s(1) and not(s(0)))
or (d(2) and s(1) and s(0));
y(3) <= (a(3) and not(s(1)) and not(s(0)))
or (b(3) and not(s(1)) and s(0))
or (c(3) and s(1) and not(s(0)))
or (d(3) and s(1) and s(0));
end arch_mux1;
-- przypisanie warunkowe - conditional signal assigment
architecture arch_mux2 of mux is
begin
with s select
y <= a when "00",
b when "01",
c when "10",
d when others;
end arch_mux2;
-- przypisanie selektywne - selected signal assigment
architecture arch_mux3 of mux is
begin
y <= a when (s = "00") else
b when (s = "01") else
c when (s = "10") else
d;
end arch_mux3;
architecture arch_mux4 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
case s is
when "00" => y <= a; -- czytamy y :=
when "01" => y <= b;
when "10" => y <= c;
--when "11" => y <= d;
y <= (others => '0');
when others => y <= d;
end case;
end process;
end arch_mux4;
architecture arch_mux5 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
if s ="00" then
y <= a;
elsif s="01" then
y <=b;
elsif s="10" then
y <=c;
else
y <=d;
end if;
end process;
end arch_mux5;
architecture arch_mux6 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
y<=(others=>'0');
if s ="00" then
y <= a;
end if;
if s ="01" then
y <= b;
end if;
if s ="10" then
y <= c;
end if;
-- if s ="11" then
-- y <= d;
-- end if;
end process;
end arch_mux6;
architecture arch_mux7 of mux is
begin
pr_if: process(a,b,c,d,s) --lista czulosci
begin
--w procesie jak najbardziej jest to prawidlowe, tylko warningi sa (LACHE - pamieci)
if s = "00" then
y <= a;
else
y <=(others => '0');
end if;
if s = "01" then
y <= b;
else
y <=(others => '0');
end if;
if s = "10" then
y <= c;
else
y <=(others => '0');
end if;
if s = "11" then -- zadziala tylko ten if bo jest sekwencyjnie ywkonywane i albo da 'd' albo 0000
y <= d;
else
y <=(others => '0');
end if;
end process;
end arch_mux7;
-- configuration conf_mux of mux is
--for arch_mux6
--end for;
--end conf_mux;
