Asynchronous reset warning issue

Question

This design contains one or more registers or latches with an active asynchronous set and asynchronous reset. While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance.

Initial_LFSR2 initial_value(RNTI,NCELL_ID,nss,nf,init) ;



always@(posedge scr_clk or posedge scr_rst) begin // Asynchronous Reset 

if(scr_rst) begin
                      LFSR1 <= 31'b1000000000000000000000000000000 ;  
                      LFSR2 <= init ;                     
                      counter <= 0 ; // reinitialized the initialzation steps counter 
                      input_counter <= 0 ; 
            end

help please

Also *"it creates a sub-optimal implementation in terms of area, power and performance."* what do you have to substantiate that statement? — Oldfart, Jun 15 '19 at 17:38
Not sure if this is your issue, but `init` looks like an input. A reset should not assign with a input value. A reset value should be a constant (a hard coded value or a parameter). — Greg, Jun 15 '19 at 22:40
The issue is that I need to store the output of a combinational logic into a register file called LFSR2 ok. and I need to implement that using asynchronous reset with out any interference of clock signal which is scr_clk. So do any one knows how I can solve that ? — A.Ashraf, Jun 16 '19 at 04:10

Greg · Answer 1 · 2019-06-18T16:30:45.707

The preferred solution is to have LFSR2 reset value be a constant. A parameter could be an expression of constants/parameters or a function with constants/parameters as inputs. It might be a bit of effort to change you code but this is what needs to be done to get "optimal implementation in terms of area, power and performance".

parameter LFSR2_INIT = initial_LFSR2_func(RNTI,NCELL_ID,nss,nf);

always @(posedge scr_clk or posedge scr_rst) begin
  if (scr_rst) begin
    LFSR2 <= LFSR2_INIT;
  end
  else begin
    LFSR2 <= next_LFSR2;
  end
end

If you absolutely must have your reset value determined by combinational logic, then there is a last resort option. It is "sub-optimal implementation in terms of area, power and performance" compared to the parameter solution, but probably will be better than what you currently have. Be warned, the more complex the logic on init, the more "sub-optimal" it will be.

This likely will not work if you are targeting for FPGA; as they tend to have limited support for flops with asynchronous set/reset. You did tag the question with xilinx which is for FPGAs. You really need to figure out why you need asynchronous set/reset at all. Try to get your code to work with only synchronous flops (no async set/reset). If you need async set/reset, then spend the extra effort to figure out how to make parameter approach work.

Because this is a last resort option, it will not be displayed by default.

Uniquify each flop of with individual async set and reset signals.
wire [LFSR2_WIDTH-1:0] lfsr2_set = {LFSR2_WIDTH{src_rst}} & init;
wire [LFSR2_WIDTH-1:0] lfsr2_rst = {LFSR2_WIDTH{src_rst}} & ~init;
genvar gidx;
generate
  for(gidx=0; gidx<LFSR2_WIDTH; gidx=gidx+1) begin : LFSR2_genblk
    always @(posedge src_clk, posedge lfsr2_rst[gidx], posedge lfsr2_set[gidx]) begin
      if (lfsr2_rst[gidx]) begin
        LFSR2[gidx] <= 1'b0;
      end
      else if (lfsr2_set[gidx]) begin
        LFSR2[gidx] <= 1'b1;
      end
      else begin
        LFSR2[gidx] <= next_LFSR2[gidx];
      end
    end
  end
endgenerate
The logic will add area. The extra routing and time to stabilize with impact performance. Stabilize time will also impact power. Power and performance will get worse if init toggles a with intermediate values while src_rst is high.

First of all, thanks so much for ur help. but there's still an error regarding the parameter solution. — A.Ashraf, Jun 18 '19 at 15:08
@A.Ashraf did you define `function integer initial_LFSR2_func(input /*inputs*/); begin /*functon body*/ end endfunction `? I appended "_func" to the name to make it clear that it is a function without defining it. — Greg, Jun 18 '19 at 15:24
definitely I created a module called Initial_LFSR2 before the main module which is called " SCRAMBLER _GP" .. when I use synchronous reset it works without any issues. but the advisor in my graduation project says what if the clock has been damaged ?!! he told me that we need to work only with asynchronous reset. and the problem cannot be solved at all — A.Ashraf, Jun 18 '19 at 15:54
@A.Ashraf , I only see a tiny bit of your code. Work with your advisor, TA, classmates, etc. — Greg, Jun 18 '19 at 18:29

Asynchronous reset warning issue

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