SystemVerilog feature "reg" encountered in Verilog context?

Question

There is an expression in my code, as in the code below. I am writing this code in Modelsim and this is a Verilog module. The compiler is giving warning, as in title. I have already searched that on internet but couldn't find any reference to that. Please note that when I remove the keyword 'parameter' this warning goes away. I must keep the keyword parameter, as I want to keep this as constant.

parameter reg  [4:0]REG_MIN = 5'b00000;   // Address of Minimum register <br/>
parameter reg  [4:0]REG_MAX = 5'b10110;  // Address of Maximum register

@iBug: why should he [get rid](https://stackoverflow.com/q/18362402/2572285) of `[4:0]`? — Qiu, Jun 14 '19 at 05:41

score 3 · Answer 1 · answered Jun 13 '19 at 18:16

3

Verilog does not allow specification of data types of parameters, but SystemVerilog does. Make sure your file has a *.sv file extension. Otherwise, parameters assume the type from the RHS.

answered Jun 13 '19 at 18:16

dave_59

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SystemVerilog feature "reg" encountered in Verilog context?

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