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I'm writing an application in order to simulate a hardware system using SystemC libraries. My problem is handling the sc_logic type. Consider a simple module

SC_MODULE(MyModule) {
   sc_in_clk clk;
   sc_out<sc_logic> outsig;
   void main_process();
   SC_CTOR(MyModule) {
      SC_METHOD(main_process);
      sensitive << clk;
   }
};

Consider the implementation of the process:

void MyModule::main_process() {
   this->outsig.write(SC_LOGIC_1);
}

OK. Problem: outsig is always '0' and never changes its value. I write many signals in my simulation but this problem occurs only with sc_logic values in sc_out ports.

Can anybody help me?

Philippe
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Andry
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  • I don't remember anything special about sc_logic. I think default value is 0, so writing SC_LOGIC_1 should trigger the output port and attached to it signal. It definitely works when I write this test case using GBL library (www.gbresearch.com/gbl). Maybe you need to check that clk is actually coming and main_process() is being called. Set a debug breakpoint in main_process. – Gene Bushuyev Jun 01 '11 at 00:54

1 Answers1

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Put sensitive << clk before SC_METHOD in the constructor.

Giovanni Funchal
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