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I can not find any flag to dump bit blasted buses. I can dump busses but I need them bit-blasted

toolic
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Sharbel Hellou
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1 Answers1

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The free IEEE Std 1800-2012 states that this is not supported:

The VCD format does not support a mechanism to dump part of a vector. For example, bits 8 to 15 ([8:15]) of a 16-bit vector cannot be dumped in VCD file; instead, the entire vector ([0:15]) has to be dumped.

You could try contacting Synopsys to see if VCS has support for this.

You could do the bit-blasting in the Verilog source code yourself for individual busses.

You could also post-process the VCD file using vcat or a free online resource such as Perl (https://metacpan.org/release/Verilog-VCD).

toolic
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  • I want to dump all bits of the bus (not part of it). Each bit should have its own signal – Sharbel Hellou May 22 '19 at 14:53
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    I offered 3 options for you. – toolic May 22 '19 at 15:08
  • I can`t upload the vcd file to the internet due to NDA. vcat does not bit blast busses. support is an option but it takes time. Splitting the busses in the Verilog file will cause a large change in the testbench – Sharbel Hellou May 22 '19 at 15:47
  • Why do you need them split up? What's wrong with busses in a VCD file? – toolic May 22 '19 at 16:03
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    vcd dumps variables same way as they are declared in verilog. you want to split the bus into separate bits, create corresponding variables in verilog. VCD is intended as a text database to be interpreted by viewers. It is a task of the viewer to manipulate bits. Find a good one. – Serge May 22 '19 at 17:30
  • I need to do a vcd diff and am using a tool that needs the busses splitted. Modelsim does have a flag to dump vcd splittted but VCS has none – Sharbel Hellou May 23 '19 at 07:51
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    So, modelsim violates the standard. choose one of the @toolic's options. – Serge May 23 '19 at 13:57