Data path on a single-cycle 32-bit MIPS processor

Question

I'm doing a homework that I need to answer signal values on marked A, B, C, D, E on the data path below which is a single-cycle 32-bit MIPS processor, however I have some questions regarding to D and E,

Suppose first four line has been executed, and that the processor is currently executing the lw instruction. The first addi instruction is located at memory address 0x00040210

addi $t0,$zero,0x3ff0
addi $t0,$t0,16
sw $t0,-8($t0)
addi $t0,$t0,12
lw $s2,-20($t0)

For D:

So it is a path after the Program Counter, and we have already executed four instructions, first instructions starts at address 0x00040210 leads to:

address 0x00040210: addi $t0,$zero,0x3ff0
address 0x00040214: addi $t0,$t0,16
address 0x00040218: sw $t0,-8($t0)
address ???: addi $t0,$t0,12
address ???: lw $s2,-20($t0)

I am stuck at the question marked address, how do I count address from there?

For E:

I am not sure how should I proceed there, hope someone can enlight me?

I'm voting to close this question as off-topic because it is not a computer programming question. It is a cpu design/electrical engineering question. — Raymond Chen, May 18 '19 at 22:16
D: MIPS instructions are always 4 bytes wide. (unless you're in MIPS16 or MicroMIPS mode on an embedded MIPS CPU that supports that...) — Peter Cordes, May 19 '19 at 03:31

Martin Rosenau · Accepted Answer · 2019-05-19T15:19:34.143

D:

There is an adder (above the letter "D" in your schematic) adding the constant 4 to the PC.

This means that the line "D" will always hold the value PC+4 - even if the current instruction is a jump or branch instruction.

And if an instruction is not a jump or branch instruction, the "D" line is fed back to through the two multiplexers at the top left of your schematic to the input of the PC register.

This means that the next value of PC will be the old value of PC+4 unless a jump or branch instruction is executed.

By the way:

The CPU in your schematic does not work like a real MIPS CPU (as they were found in WLAN routers 10 years ago).

If I understand the schematic correctly, there are only two instructions that can do a jump/branch: A variant of j and one of beq (or beqz) (both variants not using delay slots).

Using such a CPU you are not able to do subroutine calls (function calls) because there is no instruction "jumping back" to the calling function.

E:

"E" is the output of some multiplexer. If you are not performing a "MemToReg" instruction (I suppose lw is meant), the "B" signal is fed through the multiplexer.

In other words: If the current instruction is not lw, "E" and "B" are equal.

If the instruction is lw, "E" is the value stored in the RAM at address "B".

EDIT

For E, still not sure how to get that outcome though

This would really be a programming and not an electronics question. Let's look at your program:

addi $t0,$zero,0x3ff0

Now t0 contains 0x3FF0

addi $t0,$t0,16

Now t0 contains 0x4000

sw $t0,-8($t0)

The value 0x4000 is written to RAM address 0x3FF8 (Note: 0x4000-8=0x3FF8)

addi $t0,$t0,12

Now t0 contains 0x400C

lw $s2,-20($t0)

A word is read from address 0x3FF8 (Note: 0x400C-20=0x3FF8).

Two instructions above, the value 0x4000 has been written to address 0x3FF8.

For this reason, the value 0x4000 is read from RAM. And therefore the value 0x4000 is fed though the multiplexer to line "E".

Thanks for the explaination, the correct answer for D = 0x40224 and E = 0x4000. So for D when you reach 8 and PC want to +4 in the address you simple replace 8 with 4 and increase the second last number in the address by 1? For E, still not sure how to get that outcome though... — nihulus, May 19 '19 at 07:48

Data path on a single-cycle 32-bit MIPS processor

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