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I was reading a book for Digital Logic design using verilog coding and RTL synthesis. There was this sentence which is not clear to me - Latches are transparent to half of the clock cycle. Means?

kat_16
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    It is perfectly clear to me what he is asking. However the question should have been on the electronics exchange. – Oldfart May 19 '19 at 11:24

1 Answers1

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  • "Transparent" means that signal changes at the input are directly passed to the output. (Although with the inevitable delay for the signal to get through the logic).

  • Latches normaly have an input, output and enable. If the latch is 'enabled' it is 'transparent': signal changes at the input are directly passed to the output.

Using the two statements above, the sentence in the book is only true if you have a latch where the enable is connected to a clock. (And then only if he clock has a 50/50 duty cycle :-)

Therefore the sentence can not be generally seen as true.
For example here is a part of the SN7475 datasheet from TI which is a device which has four latches, but no clock. The 'C' port is the enable. You can see that the D input goes to Q and Q_bar if C is high. If C would be connected to a clock the latch would be transparent when the clock is high thus for half the clock period with a 50/50 clock.

enter image description here

Oldfart
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