1

I know that a component in VHDL is:

A reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease.

But can someone explain/show to me what components should I declare in my VHDL code in the following image?enter image description here

For example is this correct? :

architecture Behavioral of ALU1Bit is

component Adder1Bit
port(
carryIn:  IN std_logic;
A: IN std_logic;
B: IN std_logic;

output:  OUT std_logic;
F: OUT std_logic
);
end component;

begin
....
end Behavioral;
Anya Chan
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1 Answers1

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It is correct if you, for example, initialize all of the simpler components which make up the 1 bit adder. You must initialize all of the and, or, etc. components, initialize all of the internal signals and assign appropriate values for in/out.

Edit to clarify : the Adder1Bit which you declared has to be designed in some other file. In the code which you listed you are simply reusing it. In that other file, which is the design file of Adder1Bit, you must initialize all of the necessary (simpler elements such as and, or, nor, etc...) in order for the Adder1Bit to work properly.

Apollo
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