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I am writing a very very simple processor in VHDL that works with and 8-bit stream. I want to include a multiplication instruction in my ALU, but only tu multiply numbers that are inferior to 15, since a multiplication of two 8-bit numbers would result in a 16-bit number. So, for example, if I wanted to multiply 4 and 7, I would have 0000 0100 x 0000 0111, and the result would be 00011000.

So I wrote the following:

result <= std_logic_vector(unsigned(x)*unsigned(y));

But since I am working in a 8-bit system, my result signal is an 8-bit standard logic vector and ISE gives me an error message when I try to do this assignment. Since I just want the 8 least significant bits of the number, I've tried 

result <= std_logic_vector(unsigned(x)*unsigned(y))(7 downto 0);

But then it says that I can't index the result of a type conversion, which seems clear but it doesn't point out any other way to do it.

Is there any way to pick the least significant bits of a multiplication without having to create a separate signal?

Thanks in advance.

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1 Answers1

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After some searching I've come to believe that the answer to the question "Is there any way to pick the least significant bits of a multiplication without having to create a separate signal?" is no, since I can't index a function like std_logic_vector.

This has to be done creating an intermediary signal, like

mult <= std_logic_vector(usigned(x) * unsigned (y));

And then

result <= mult(7 downto 0);
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  • *Is there any way to pick the least significant bits of a multiplication without having to create a separate signal?* `result <= std_logic_vector("*"(unsigned(x),unsigned(y))(7 downto 0));` This works because overload operators are defined as functions, the "*" function presumably found in package numeric_std (lacking declarations and use clauses). IEEE Std 1076-2008 4.5.2 Operator overloading. Here the function is called instead of using the operator. A function call can be used as the prefix of a slice name, 8. Names 8.1, 8.5 Slice names. –  May 07 '19 at 07:53
  • @user1155120: smart, but not exactly what I call 'readable'. Maybe an explicit resize would be more intuitive: `result <= std_logic_vector(resize(unsigned(x) * unsigned(x), 8));` ? – mfro May 07 '19 at 08:17
  • *readable* would be a stretch for the shown resize call as well with all the type conversions. There's package numeric_std and type unsigned for an unsigned binary value or numeric_std_unsigned for treating std_logic_vector values as unsigned. Any named one-dimensional array object can be sliced as a basic operation without dynamically elaborating named objects in a resize function call (two variables and an alias). Evaluating a slice name can be less effort than elaborating an alias. –  May 07 '19 at 09:43