Weird error when running the test bench, I have never seen this before. I am attempting to simulate an 8-bit calculator with 4 registers. The calculator has 8 bit instructions for add,subtract, branches on equal, load immediate, and print to the monitor. I've checked to make sure I am not in any infinite loops. I've researched online, and there does not seem to be any specific reasons why I may have this error.
I've triple checked for loops, memory leaks, and also tried increasing the stack frame. None have worked out so far. Using commands ghdl -a, -e, and -r to analyze, compile, and run.
'''
architecture structural of calculator_tb is
component calculator is
port(
I : in std_logic_vector(7 downto 0); --instruction input
clk : in std_logic
);
end component calculator;
signal I : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
calculator_0 : calculator port map(I, clk);
process
file instruction_file : text is in "instructions.txt"; --Instructions in text(ASCII) file.
variable instruction_line : line;
variable intruction_vector : bit_vector(7 downto 0);
begin
while (not(endfile(instruction_file))) loop --Loop to the end of the text file.
wait for 1 ns;
clk <= '0';
readline(instruction_file, instruction_line); --Read in instruction line
read(instruction_line, intruction_vector); --merge instruction to bit vector
I <= to_stdlogicvector(intruction_vector); --Convert bit vector to std_logic_vector and pass instruction to the calculator input.
--Create a rising edge for the clock.
wait for 1 ns;
clk <= '1';
end loop;
assert false report "end of test" severity note;
end process;
end architecture structural;
''''
The runtime error I receive is:
invalid memory access (dangling accesses or stack too small)
