I'm confused about comparing number of stall cycles of pipelining with and without data forwarding.
I'll use an example to illustrate my question:
For the following MIPS instructions:
I1: add $t1, $t2, $t3
I2: sub $t2, $t1, $t2
Which of the following pipeline is true? ("S" indicates one clock cycle stall)
I1 IF ID EX MEM WB
I2 IF S S S ID EX MEM WB
I1 IF ID EX MEM WB
I2 IF S S ID EX MEM WB
To be more specific, when data forwarding is not applied, does Instruction Decode happen in the same clock as Write Back, or one clock after?
