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Im new to vhdl and im trying to created a 8-bit frequency divider using a similar or same concept presented on the image.. can anybody help me. 4bitfrequency divider

Lewis Atauchi
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    You would be better served asking such questions on https://electronics.stackexchange.com/ – Rob Apr 16 '19 at 17:48

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I think an extension of the existing is sufficient. You have to do the following things:

  1. Add 4 extra Q's : Q4, Q5, Q6 and Q7 as out std_logic.

  2. Change signal "count" from (3 downto 0) to (7 downto 0).

  3. Change the 4-bit value "0000" to "00000000" at reset.

  4. After end process you have to add the same as point 1 --> Q4 <= count(4); etc.

That's all you have to do I think.

Joost
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  • This is easiest way to achieve this goal. But if you are doing whit learning purposes, you could add generic parameters and replace all your Q's outputs by onle one Q. `generic ( N : integer); --Scaling Factor` And you should define you count as 'signal count : unsigned (N downto o);' and your output as `Q <= count(N)` – tarekasis Apr 17 '19 at 08:18
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    That's indeed a better and more efficient way, but I think if you are not familiar with VHDL, it is better that you first understand what is happening. After that you can focus on efficient programming. – Joost Apr 17 '19 at 08:30