how to know the circuit is minimum or not？

Question

1.When using a karnaugh map to simplify a circuit，how to know if the circuit is minimum or not？

2.If the expression can be turned into multi-level，how to know how many levels could be minimum circuit？(minimum "inputs" and "gates")

Answer 1

Optimality for two-level design:
In a Karnaugh map, there may be prime implicants which cover minterms not covered by any other implicant. These are called essential, as they have to be part of any selection of prime implicants which represents the circuit.

Non-essential prime implicancts may or may not be part of the selected cover. There is a choice, which non-essential one(s) to pick. Therefore, it is not always obvious, how many prime implicants have to be selected to cover all minterms. But in practical cases with only four or fewer input variables, there is typically little doubt. However, in general cases with many input variables, the set cover problem to solve can take arbitrarily long.

Multilevel is much harder:
Multilevel logic synthesis is a research topic since decades. No algorithm is known which always finds an optimal circuit.

The optimization criteria vary depending on the application. Number of gate levels may be less relevant than the physical time delay between input and output change. The delay in turn depends on the gate technology being used and the fan-out of gate inputs driven. Other criteria include chip area and number of 74xx-series integrated circuits required.