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I am looking at some Verilog stuff from 'asic-world' and have a question about the asynchronous reset. Not very sure how does it work when the reset is at its positive edge. If only consider the rising edge of reset, the Verilog code below check whether reset is equal to 1 for resetting. If reset is 1, then output gets reset to ZERO. But since it happens at the rising edge of reset, reset is in a metastable state, which is neither 0 nor 1. So, checking the value of reset at the positive edge of reset does not really make sense to me. Could anyone please explain it?

Verilog code from Asic-world:

module  asyn_reset(clk,reset,a,c);
    input clk;
    input reset;
    input a;
    output c;    

    wire clk;
    wire reset;   
    wire a;    
    reg c;  

    always @ (posedge clk or posedge reset)
    if ( reset == 1'b1) begin
        c <= 0;
    end else begin
        c <= a;
    end
    endmodule
Greg
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Davy John
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1 Answers1

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Asynchronous reset means that your circuit should reset whenever reset signal is active 'Irrespective' of clock. Naturally, this should be included in the sensitivity list as such syntax makes it considered as async reset. Note that it does not require an active clock to bring flip-flops to a default (reset) state, and You should not be concerned by any metastability issue when entering reset state. The very first block of always process (that checks reset input state) is needed here and you need to adhere to such coding style. The most important point is the relative timing between clock and reset can be ignored during Reset Assertion. The Reset Release MUST be synchronized to the clock as it indeed can lead to metastability issues. There are known circuits that can be utilized for async reset release procedure (these are a bit specific but widely used in the ASIC's world so you should be able to find reference materials via google browser).

Greg
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PrzemekS
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