Is there a way to warn wrong clock domain crossing in Chisel3?

Question

As I read from Chisel wiki, it is possible to declare several clock domain in a single module.

But if we need to read/write a signal through two different clock domains it's important to manage metastability (with dual d-latch, asynchronous fifo, ...).

If we don't manage it, it's a design error. Is there a way to ask chisel checking wrong clock domain crossing in design ?

score 1 · Accepted Answer · answered Apr 08 '19 at 19:35

1

Not at the moment. This is a needed, but as of yet unimplemented feature.

answered Apr 08 '19 at 19:35

Jack Koenig

5,840
15
21

1

Ok, I added the request on github : https://github.com/freechipsproject/chisel3/issues/1085 – FabienM Apr 30 '19 at 09:07

Is there a way to warn wrong clock domain crossing in Chisel3?

1 Answers1