How 32-bit word would be stored in 16-bit architecture that does not detect overflow?

Question

How would a 32-bit numeric codeword be stored in a hypothetical 16-bit architecture if this system cannot detect the overflow?

How would it be stored in a real 68HC11 system?

What confuses me is that in the system that does not detect the overflow, I am not sure if it is possible to store the value larger than 16 bits at all?

Isn't 6811 an 8-bit architecture, not 16-bit? Also, overflow isn't about storage, but about the results of performing certain operations on the registers. You can easily store 32-bits into two 16-bit registers. Overflow comes into play when you perform an operation, such as addition, on two 16-bit operands in that case. The 6811 has the condition code register (CCR) that does indicate whether there is an overflow. — lurker, Mar 29 '19 at 11:01
Thank you for your answer! Probably my question is not completely clear, I am talking about two computer architectures: 16 bit and 6811. Could you possibly provide me with an example of how a 32-bit numeric code word would be stored in a 16-bit architecture? Thanks a lot again. — Kristina Cer, Mar 29 '19 at 11:05
What does a 6811 have to do with 16-bit or 32-bit architectures? That's why I'm confused. I'm also confused about why you're saying there's no overflow indicator, so I am supposing that's a totally hypothetical situation? A 32-bit value can be stored in two 16-bit values. You put the high 16 bits in one register, and the lower 16 bits in another. — lurker, Mar 29 '19 at 11:08
Yes, this question is purely for learning purposes, the hypothetical 16-bit system is designed without the overflow indicator, and it is compared with the 6811 system. If I understand correctly, both systems will simply store a 32-bit word in 2 16 -bit or 4 8-bit registers depending on a system? — Kristina Cer, Mar 29 '19 at 11:21
@KristinaCer Correct. Whether there is an overflow flag or not doesn't matter in this regard. — fuz, Mar 29 '19 at 11:26
Concerning the operations, they are performed in several steps on these registers. An overflow or carry out flag helps a lot for carry propagation, but it is not required. You can find it thanks to the mathematical properties of numbers. For instance, when adding two unsigned, if result is lower than one of the operands, you have a carry out. — Alain Merigot, Mar 29 '19 at 11:46

score 3 · Answer 1 · answered Mar 29 '19 at 14:21

One thing has nothing to do with another, 32 bit as well as 16 bit x86 processors could handle 64 bit variables long before the 64 bit processors came out. 8 bit processors can handle a million bit variables, so long as there is enough memory for storage.

int fun0 ( void )
{
    return(sizeof(unsigned long long));
}

unsigned long long fun ( unsigned long long a, unsigned long long b )
{
    return(a+b);
}

compiled for a 16 bit target:

00000000 <fun0>:
   0:   3f 42           mov #8, r15 ;r2 As==11
   2:   30 41           ret         

00000004 <fun>:
   4:   1c 51 02 00     add 2(r1),  r12 ;0x0002(r1)
   8:   1d 61 04 00     addc    4(r1),  r13 ;0x0004(r1)
   c:   1e 61 06 00     addc    6(r1),  r14 ;0x0006(r1)
  10:   1f 61 08 00     addc    8(r1),  r15 ;0x0008(r1)
  14:   30 41           ret

That instruction set has no problem with infinite (well until you run out of storage) sized variables.

In grade school we learned how to deal with this

 99
+ 5
====

we dealt with this one digit at a time, our hand done math is one digit wide yet we could handle infinitely large numbers so long as we have enough paper.

we did this single digit math

  9
+ 5
====
 14

which is 4 carry the 1

then we did this single digit wide math

  1
  9
+ 0
======
 10

which is 0 carry the 1

so then we did this single digit math

  1
  0
+ 0
====
  1

finally getting the result 99 + 5 = 104

no difference when using a computer other than base 2 is easier than base 10.

as far as storage goes 32 bits is 32 bits if you have room to store 32 bits then you can store 32 bits. you can read those bits operate on them directly or through registers depending on the instruction set...how you store them is up to you or if you use a compiler they have already decided how they are doing it. — old_timer, Mar 29 '19 at 14:23
Thank you very much @old_timer for your answer. I was thinking that if the hypothetical 16-bit system that uses two's complement code does not have a mechanism to detect the overflow, there is a limit of the numbers I can operate with? If, for example, I'd like to add two numbers that would result in a 17-bit codeword, I'd get a wrong answer since there's no way to detect the overflow in this case? — Kristina Cer, Mar 30 '19 at 16:53
@KristinaCer In your theoretical CPU "there's no way to detect the overflow" automatically. But you can still calculate it 'manually'. The 68HC11 being an 8/16 MCU as it has both 8-bit and 16-bit accumulator and ADDD will adjust the CCR[C] on overflow. You can emulate as CCR[C] = D15 • M15 + M15 • /R15 + /R15 • D15 where D= ACCD, M=Memory, R=Result — tonypdmtr, Mar 30 '19 at 18:04
@old_timer Storage is usually based on the default CPU endian-ness; the 68HC11 being big endian will have the most significant bytes/words in lower addresses — tonypdmtr, Mar 30 '19 at 18:05

score 3 · Accepted Answer · edited Mar 30 '19 at 09:15

how a 32-bit numeric codeword would be stored in a 16-bit architecture ...

Simply storing information does not require any features of the CPU.

For storing N bits of data, you require N/8 bytes of memory.

It is the software (and not the hardware) that must "know" if four bytes contain one 32-bit word, a 32-bit floating-point value, two 16-bit words, 4 8-bit words or 32 single bits.

If you write a program in assembler, you have to write the program accordingly. If you use some programming language, the compiler must do this.

... if this system cannot detect the overflow?

Calculation (especially adding) is a different thing. If you refer to the "carry flag" by the word "overflow":

You can manually check for a carry: If you add two numbers and there is a carry out, the sum will be smaller than each of the two summands. If there is no carry, the sum will be larger or equal to each summand.

When you perform a 64-bit addition on a MIPS CPU (a 32-bit CPU not supporting a carry flag) using the GCC compiler, this check will be done. Here the pseudo code:

sum_low  = a_low + b_low
  // The CPU does not support carry:
sum_high = a_high + b_high
  // Simulate carry:
if(a_low > sum_low) sum_high = sum_high + 1

How would it be stored in a 6811 system?

As far as I know the 6811 uses "big endian" storage. This means that the CPU itself stores 16-bit words (like the program counter) in a way that the high 8 bits are stored at an address N and the low 8 bits are stored at address N+1.

For this reason, most compilers would also store a 32-bit word "big endian": The high 8 bits are stored at address N and the low 8 bits are stored at address N+3.

The 6811 definitely supports a "carry flag", adding with carry-in and an "overflow flag". So an 6811 is not an example of a CPU "not detecting an overflow". See old_timer's answer how adding works on CPUs that have overflow and carry.

How 32-bit word would be stored in 16-bit architecture that does not detect overflow?

2 Answers2