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What is an alternative to save a word from register into RAM? For example i can explain lw command as lui, ori. How could be 4 Bytes stored into RAM without using sw?

dancingsushi
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    No you can't. `lw` is not the same as `lui` and `ori`. You are probably thinking of `la`. – Jester Mar 28 '19 at 19:17
  • Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw. – dancingsushi Mar 28 '19 at 19:34
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    No you can not do the same with `lui` and `ori`. `lw` accesses memory, the alternatives don't. You can only use `lui/ori` to load a known compile-time constant. `lw` reads memory. Tell me, how do you write for example `lw $a0, ($t0)` using `lui/ori`? – Jester Mar 28 '19 at 19:36
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    _"How could be 4 Bytes stored into RAM without using sw?"_ By using 4 `sb` instructions, or 2 `sh` instructions. – Michael Mar 28 '19 at 20:45

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First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.

MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).

Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.

In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.

In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.

These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).

http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.

So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.

Footnote 1: MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.

See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.

Peter Cordes
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