How to declare inputs and outputs when it's opposite for different modules in a processor in verilog?

Question

module alucontrol(iw,cntrl,Ra,Rb,Wa);
input [14:0]iw;
output reg [3:0]cntrl;
output reg [3:0]Ra;
output reg [3:0]Rb;
output reg [3:0]Wa;

always@(*)
begin
cntrl=iw[14:12];            
Ra=iw[11:8];
Rb=iw[7:4];
Wa=iw[3:0];
end

endmodule
////////////////////////////////////////////
module alumemory(Ra,Rb,Wa,A,B);
input wire [3:0]Ra,Rb,Wa;
output reg [3:0]A,B;

reg [3:0]  mem [0:15]; 
reg array[3:0][0:15];

always@(*)
begin
array[3:0][0]=4'b0100;
array[3:0][1]=4'b1001;
array[3:0][2]=4'b0110;
array[3:0][3]=4'b0010;
array[3:0][4]=4'b0100;
array[3:0][5]=4'b1101;
array[3:0][6]=4'b0100;
array[3:0][7]=4'b0001;
array[3:0][8]=4'b0000;
array[3:0][9]=4'b1111;
array[3:0][10]=4'b1000;
array[3:0][11]=4'b1001;
array[3:0][12]=4'b1000;
array[3:0][13]=4'b1011;
array[3:0][14]=4'b1100;
array[3:0][15]=4'b1010;
end

integer my_int1;
always@(1)
begin
my_int1=Ra;
A[3:0]=array[3:0][my_int1];
end 

integer my_int2;
always@(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end

integer my_int3;
always@(1)
begin
my_int3=Wa;
array[3:0][my_int3]=C[3:0];
end


endmodule
////////////////////////////////////
module Decoder(cntrl[3:0],adden, suben, mulen, diven, anden, oren, xoren, noten);
 input [3:0]cntrl;
 output adden, suben, mulen, diven, anden, oren, xoren, noten;
 assign adden=(~a&~b&~c),
    suben=(~a&~b&c),
    mulen=(~a&b&~c),
    diven=(~a&b&c),
    anden=(a&~b&~c),
    oren=(a&~b&c),
    xoren=(a&b&~c),
    noten=(a&b&c);
endmodule
//////////////////////////////////////////////////
module alu_arith(input[3:0]A,
input adden, input suben,input mulen,input diven,input anden,input oren,input xoren,input noten,
input[3:0]B,
output reg [7:0]C
);
reg cntrlinp[7:0];
//wire[3:0]A;
//wire[3:0]B;
assign cntrlinp[0]=adden,
       cntrlinp[1]=suben,
        cntrlinp[2]=mulen,cntrlinp[3]=diven,cntrlinp[4]=anden,cntrlinp[5]=oren,cntrlinp[6]=xoren,cntrlinp[7]=noten;
always@(*)
begin
case(ctrlinp[7:0])
00000001:C=A+B;
00000010:C=A-B;
00000100:C=A*B;
00001000:C=A/B;
00010000:C=A&B;
00100000:C=A|B;
01000000:C=A^B;
10000000:C=~A;
default: C=8'b00000001;
endcase
end
 
endmodule

///////////////////////////////////////////////////////

module testbench;
reg[14:0]iw;
wire[7:0]C;

alucontrol a1(iw, cntrl,Ra,Rb,Wa);
alumemory a2(Ra,Rb,Wa,A,B);
alu_arith a3(A,B,C);
Decoder a4(cntrl,adden, suben, mulen, diven, anden, oren, xoren, noten);

initial begin
 $display("time\t A  B  cntrl  C");
    $monitor("%g\t %b %b %b %b",
    $time, A, B, cntrl, C);
 
 #0  C=8'b00000000;
  iw=15'b101000101011010;
 #5  iw=15'b001100110011001;
 #10 iw=15'b010101110101110;
 end
 
  
endmodule

So i'm trying to make a very basic design of a processor(a simple ALU with register file and control unit) where the control unit takes the opcode, divides it into iw(instruction word), Ra(Read A),Rb(Read B) and Wa(Write A) and sends the last three of those to the register file to write/read registers.

The parameters that are output for control unit are input for register file, and my code is repeatedly giving the following error in two lines after alumemory module begins:

syntax error
error: Invalid variable list in port declaration.

I don't understand what's exactly causing a syntax error. Please help.

I've created a 2d array for register file and I'm accessing it using the following block:

integer my_int2;
always@(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end

I think I've declared ports and wire and reg in an appropriate way.

module alucontrol(iw,cntrl,Ra,Rb,Wa);
input [14:0]iw;
output [3:0]cntrl;
output[3:0]Ra;
output[3:0]Rb;
output[3:0]Wa;
reg [3:0]Ra; 
reg [3:0]Rb; 
reg [3:0]Wa;
reg [3:0]cntrl;

always@(*)
begin
cntrl=iw[14:12];            
Ra=iw[11:8];
Rb=iw[7:4];
Wa=iw[3:0];
end

endmodule
////////////////////////////////////////////
module alumemory(Ra,Rb,Wa,A,B);
input [3:0]Ra,input [3:0]Rb;input [3:0]Wa;
output[3:0]A;output [3:0]B;
wire [3:0]Ra; wire [3:0]Rb; wire [3:0]Wa;
reg[3:0]A;
reg[3:0]B;
reg [3:0]  mem [0:15]; 
reg array[3:0][0:15];

always@(*)
begin
array[3:0][0]=4'b0100;
array[3:0][1]=4'b1001;
array[3:0][2]=4'b0110;
array[3:0][3]=4'b0010;
array[3:0][4]=4'b0100;
array[3:0][5]=4'b1101;
array[3:0][6]=4'b0100;
array[3:0][7]=4'b0001;
array[3:0][8]=4'b0000;
array[3:0][9]=4'b1111;
array[3:0][10]=4'b1000;
array[3:0][11]=4'b1001;
array[3:0][12]=4'b1000;
array[3:0][13]=4'b1011;
array[3:0][14]=4'b1100;
array[3:0][15]=4'b1010;
end

integer my_int1;
always@(1)
begin
my_int1=Ra;
A[3:0]=array[3:0][my_int1];
end 

integer my_int2;
always@(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end

integer my_int3;
always@(1)
begin
my_int3=Wa;
array[3:0][my_int3]=C[3:0];
end


endmodule

I notice a comma in your port declaration for alumemory: `input [3:0]Ra,input...` Also that way of defining ports has been superseded for a looong time. — Oldfart, Mar 24 '19 at 06:18

score 1 · Answer 1 · answered Mar 24 '19 at 15:18

1

Declare your ports this in this much simpler way:

module alumemory(
  input wire [3:0] Ra, Rb, Wa, 
  output reg [3:0] A,B
);
  reg [3:0]  mem [0:15]; 
  reg array[3:0][0:15];
  ...

answered Mar 24 '19 at 15:18

dave_59

39,096
3
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Thanks, I did, but that doesn't solve the issue. Running the code still shows a ton of errors. I suspect it's due to improper declaration of reg and wire. Would be really thankful if you can have a look at it. I've updated the question to contain the full code I wrote. Thanks!! – Vaibhavi Rastogi Mar 25 '19 at 06:52
As you just mentioned, you have tons of errors. Please start fixing them and ask question about the errors which you have issues with. The one you asked about will be fiixed by removing the comma (see reply to the original message) or with dave's suggestion. – Serge Mar 25 '19 at 13:59

How to declare inputs and outputs when it's opposite for different modules in a processor in verilog?

1 Answers1