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Consider you have an SPI bus with only a single chip select. Is there a chip such that I can connect 8 or more devices to that SPI bus?

To simplify things, you may assume that all devices agree on the SPI mode (data needs to be valid on a rising edge). Also, all devices are of the time, where chip selects stays low for the whole transfer, and is not toggled after each word.

The SPI multiplexer could have 4 inputs:

  • MISO, MOSI, input clock, master chip select

and 9 outputs:

  • output clock, 8 slave chip selects

MISO and MOSI are connected directly to the slaves. The slaves have their SPI clock connected to the output clock and their chips selects are connected to one of the 8 slave chip selects.

The SPI multiplexer would take the two bytes of each SPI transfer as its own input. The first byte could indicate which slave is to be selected. For configuration of the multiplexer, a ninth address could be allowed.

If one of the 8 slaves is selected, the multiplexer would then activate the slave's chip select after the first byte (or even after the first few bits of the first byte). The output clock would activate with the start of the second byte and it would be synchronous to the input clock. Leaving the clock inactive during the first byte makes sure that the slaves never take notice of the first byte.

Such a chip does not seem to exist. I found solutions with two chip selects, but that's not an option to upgrade old hardware designs with just a single chip select.

Does such a thing exist?

Sven
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1 Answers1

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It does not exist because there is no need for it. Often CS is only controlled from software as a regular gpio before initiating an SPI transfer, then you could just wire the different slaves to different GPIO and use them as CS. If the CS is generated and needed by the hardware block you gate this signal with the external chip select to choose the wanted slave.

Your proposed one byte to select bus would also break all software which relay on writing from and reading to the same buffer, and it would be decrease the available bandwidth with control signals.

As a side note with recent development with secure enclaves and Trustzone the trend is not to share spi buses but rather hard wire them so only code running in the trusted part of the SoC will be able to access the connected slave.

Simson
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    Lets assume you designed a connector for a daughter board. The pin-out gives you 2 CS lines. Now you want to have 3 chips on the daughter board, each of them being an SPI slave. What then? Yes, I could use a microcontroller. But that is too complex, to be honest, for such a simple task. – Sven Jun 13 '20 at 05:22
  • @Sven a 2->4 line demultiplexer would be perfect. It would even leave one output for no slave activated. Something like a 74xx138 would work nicely with no other components since it has active low outputs (although that could handle eight devices). – Tuomas Laakkonen Aug 12 '21 at 01:29