VHDL Pulse Generation with External Trigger and Trigger Out

Question

I am stuck in this program to create a custom pulse from external trigger and internal trigger.

Here is my program for external trigger. It will take a trigger signal from "trig_in" input port to generate a custom pulse:

if state_trig = extrig then
    if (trig_in = '1') then
        counter1 <= "000000";
            if(counter >= 1 and counter <= 2) then
                pwm_out1 <= '1';
                pwm_out2 <= '0';
            end if;
            if(counter > 2 and counter <= 600) then
                pwm_out1 <= '0';
                pwm_out2 <= '0';
            end if;
            if(counter > 600 and counter <= 3000) then
                pwm_out1 <= '1';
                pwm_out2 <= '1';
            end if;
        counter <= counter + 1;
    else if (trig_in = '0') then
        counter <= "000000";
        counter1 <= counter1 + 1;
            if (counter1 >= 2100) then
                pwm_out1 <= '0';
                pwm_out2 <= '0';
            end if;
        end if;
    end if;
end if;

And here is the program for internal trigger. It will generate a 1kHz repetition pulse to trigger out on "trig_out" output port:

if state_trig = intrig  then
    --1kHz
        if(i >= 1 and i <= 2) then
            pwm_out1 <= '1';
            pwm_out2 <= '0';
        end if;
     if(i > 2 and i <= 600) then
            pwm_out1 <= '0';
            pwm_out2 <= '0';
        end if;        
     if(i > 600 and i <= 3000) then
            pwm_out1 <= '1';
            pwm_out2 <= '1';
        end if;      
     if(i > 3000) then
            pwm_out1 <= '0';
            pwm_out2 <= '0';
        end if;
        if(i = 300000) then i := 0; end if;
        i := i + 1; 
    end if;
end if;

I use the fsm state to determine for "extrig" and "intrig" state.

 type    fsm_trig   is (none, intrig, extrig);
 signal state_trig : fsm_trig := none;

Two programs work separately perfect. But when i put both of them in one process (clock). The pulse which is generated in each trigger program conflicts each other. I am using UART to determine the state of trigger. Two signal "pwm_out1" and "pwm_out2" are assigned to output ports to generate the pulse:

out_clk1 <= pwm_out1;
out_clk2 <= pwm_out2;

Here are ports for two programs:

    sys_clk     : in   STD_LOGIC;           --system clock
    rx          : in     STD_LOGIC;         --receive for UART
    trig_in     : in   STD_LOGIC;           --External trigger
    trig_out : out  STD_LOGIC;              --Internal trigger
    out_clk1 : out  STD_LOGIC;              --Pulse out1
    out_clk2 : out  STD_LOGIC;              --Pulse out2

Please give me any idea to avoid the conflicts between two programs. Thanks in advance.