Approach to design valid/ready handshake

Question

I have implemented valid/ready handshake signals in verilog. I just wanted to know if my approach is right or something is wrong. I shall be happy to know of any improvement. A simple counter is used as an input to fifo. So when fifo is almost full which is declared when used word of fifo is 8 (8 stacks of fifo are used out of 16), ready is zero.

Here is the code.

module fifohandshake(
input CLK,
input RST,
input [31:0] INPUT,
output [31:0] OUTDATA,
output [3:0] usedword,
output Writereq,
input RDReq,
output Almost_full,
output EMPty,
output FUlL,
output VALID,
output READY
);

reg valid;
reg ready;
reg WRReq;

assign VALID=valid;
assign READY=ready;
assign Writereq=WRReq;

fifoip u0(
    .clock(CLK),
    .data(INPUT),
    .rdreq(RDReq),
    .sclr(RST),
    .wrreq(WRReq),
    .almost_full(Almost_full),
    .empty(EMPty),
    .full(FUlL),
    .q(OUTDATA),
    .usedw(usedword)
);


always @(posedge CLK)
    begin
            if(INPUT)
                begin
                    valid<=1;
                end
            else
                begin
                    valid<=0;
                end
    end

always @(posedge CLK)
    begin
        if(Almost_full)
            begin
                ready<=0;
            end
        else
            begin
                ready<=1;
            end
    end

always @(posedge CLK)
    begin
        if(ready)
            begin
                WRReq<=1;
            end
        else
            begin
                WRReq<=0;
            end
    end
endmodule

Have I done it in a right way or is there something that I need to correct? Here are the waveform results. enter image description here

score 0 · Answer 1 · answered Mar 06 '19 at 08:45

For those who think that I didn't put enough effort in my research. A finite state machine is a good approach to implement ready/valid handshake protocol. Few points have to be kept in mind

The valid signal doesn't depends upon ready signal. In other words there shouldn't be a combinational loop if you trace your logical circuit from valid to ready signal.

Three basic states can be defined for valid/ready protocol. First idol state where there is no valid data even though the slave is ready to accept data. Then, a transfer state where both ready and valid signals are high. And the third state is wait state where we have the valid signal high but ready signal is low.

A buffer (a fifo or a simple register) has to be used in the wait state to buffer the valid data in case the slave is no ready. Hence, data is not lost and is still on the data line whenever slave is again ready.

That's it....

This was the help that I was trying to ask from the community but from the last couple of days whenever I post something someone intentionally mark my question to be -1. I hope not to experience it next time...

Approach to design valid/ready handshake

1 Answers1