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I am trying to interface the output of my FPGA onto a DAC. I am using the PmodDA2 DAC. The trouble I am having is working out how to output the data from a 16bit register into 1 bit per clock cycle.

I have studied the timing diagram and understand that CS needs to send a pulse before data transmission begins.

I have tried using the necessary resets and other features as applicable within my design as a whole.

I tried implementing a count to cycle between 0 to 16/17 and when it was at the beginning it would set CS to high and begin transmission. However I did not believe this would be at all the correct way to do it.

 architecture Behavioral of DAC is
 signal count : integer range 0 to 15;
 signal selected : std_logic;
 signal data_storage : std_logic_vector(15 downto 0);

 begin

 process(D_DAC, CE_DAC, RES_DAC, RES_DAC, data_storage)
 begin
 if RES_DAC = '1' then
    data_storage <= "0000000000000000";
end if;

 if rising_edge(CLK_DAC) then
        if CE_DAC = '1' then
        data_storage <= D_DAC;          
        end if;

    end if;
    end if;


end process ;
CS_DAC <= CE_DAC;
SCLK_DAC <= CLK_DAC;
DATA1_DAC <= data_storage;
end Behavioral;

I'm getting myself very confused over this.

I'd appreciate any help.

************************EDIT************************

I have had another go at implementing the counter...

process(D_DAC, CE_DAC, CLK_DAC, RES_DAC, data_storage)
 begin
     if RES_DAC = '1' then
        data_storage <= "0000000000000000";
        cound <= 0;
        selected <= '0';
    elsif rising_edge(CLK_DAC) then 
        if CE_DAC = '1' then                
            if count = 0 then
                selected <= '1';
            end if;
            if selected = 1  then
                if count = 15 then
                    count <= 0;
                    selected <= '0';
                else
                count <= count + 1;
                data_storage <= D_DAC;          
        end if;
        end if;
    end if;
    end if;

end process ;
CS_DAC <= CE_DAC;
SCLK_DAC <= CLK_DAC;
DATA1_DAC <= data_storage;
end Behavioral;
Paul James
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  • You need to take a step back and think what hardware you are trying to build. Your code includes a clock, but you haven't followed the templates for sequential logic. See [this answer here](https://stackoverflow.com/questions/36539962/errorxst827-signal-count-cannot-be-synthesized-bad-synchronous-description/36543625#36543625). – Matthew Taylor Feb 14 '19 at 11:07
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    See [PmodDA2 Example Code](https://reference.digilentinc.com/pmod/pmod/da2/example_code), specifically [Generic VHDL](https://reference.digilentinc.com/_media/pmod/pmod/da2/pmodda2_refcomp.zip) for an example. Your snippets aren't conveying enough information for your readers, particularly without any port declarations. You're also no clearly describing the problem you're having doing what exactly. Where is this timing diagram to which you refer? –  Feb 14 '19 at 12:49
  • You need to follow @user1155120's advice and to stick to the templates I described in the answer I linked to specifically `CLK_DAC` and `RST_DAC` should be in the sensitivity list, that's it. – Matthew Taylor Feb 14 '19 at 14:10
  • See IEEE Std 1076-2008 11.3 Process statement. Applying the rules in 10.2 Wait statement for `all` producing the sensitivity list set would also add `count` and `selected`( but not `data_storage`). Streamlining the sensitivity list can be no big deal for synthesis eligible code. Ordering the sensitivity list allows resuming based on sensitivity list signals to the right use of cached left signal values. The outer If statement conditions would not evaluate TRUE suspending the process in the same implicit wait statement where the sensitivity list is evaluated for resuming. –  Feb 14 '19 at 20:38

0 Answers0