VHDL coding error “Else clause after check for clock not supported”

Question

The function of the code is given an opcode, it will perform a task at the rising edge of the clock. I'm a second year undergrad student, so any help/input will be appreciated

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is   Port (
   X,Y     :IN BIT_VECTOR(2 downto 0);
   OPcode  :IN BIT_VECTOR(2 downto 0);
   Z       :OUT BIT_VECTOR(5 downto 0);
   CLK     :IN BIT;
   TempValX:INOUT BIT_VECTOR(5 downto 0)); 
end ALU;
architecture Circuit of ALU is signal g: BIT_VECTOR(3 downto 0);
signal C: BIT_VECTOR(3 downto 0);
signal p, u, r : bit_vector(2 downto 0);
signal s: Bit_vector(5 downto 0);
Component ThreeBitFA is
       PORT (X,Y   :IN BIT_VECTOR(2 downto 0);
               C   :INOUT BIT_VECTOR(3 downto 0));
   end component; begin adder:ThreeBitFA port map(
           X => X,
           Y => Y,
           C => C);
Process(X,Y,CLK,OPcode)
begin
     IF OPcode = "000" THEN ----------------ADD OPcode
       IF (CLK'EVENT AND CLK = '1') THEN
           tempvalx <= "00" & C;
                     Z <= tempvalx;
       end if;
     ELSIF OPcode = "001" THEN ----------------MULT OPcode
       IF (CLK'EVENT AND CLK = '1') THEN
          IF Y(0) = '1' THEN P <= X; ELSE P <= "000"; END IF;
          IF Y(1) = '1' THEN u <= X; ELSE u <= "000"; END IF;
          IF Y(2) = '1' THEN R <= X; ELSE R <= "000"; END IF;
       z(0) <= P(0); 
       z(1) <= P(1) XOR u(0); s(0) <= P(1) AND u(0);
       z(2) <= P(2) XOR u(1) XOR R(0) XOR s(0); s(1) <= s(0) AND P(2); s(2) <= u(1) AND R(0);
       z(3) <= u(2) XOR R(1) XOR s(1) XOR s(2); s(3) <= s(2) AND s(1); s(4) <= u(2) AND R(1);
       z(4) <= R(2) XOR s(3) XOR s(4); s(5) <= s(3) AND s(4); 
       z(5) <= s(5);
       end if;

     ELSIF (OPcode = "010") THEN ------------AND OPcode
       IF (CLK'EVENT AND CLK = '1') THEN
           Z <= "000" & (X AND Y);
       end IF;
     ELSIF (OPcode = "011") THEN ------------OR  Opcode
       IF (CLK'EVENT AND CLK = '1') THEN
           Z <= "000" & (X OR Y);
       end IF;
     ELSIF (OPcode = "100") THEN ------------XOR Opcode
       IF (CLK'EVENT AND CLK = '1') THEN
           Z <= "000" & (X XOR Y);
       end IF;
     ELSIF (OPcode = "101") THEN ------------NOT Opcode
       IF (CLK'EVENT AND CLK = '1') THEN
           Z <= "000" & (NOT X);
       end IF;
     ELSIF (OPcode = "110") THEN -----------Rshift OPcode
       IF (CLK'EVENT AND CLK = '1') THEN
           TempValX <= "000" & X;
           Z <= '0' & TempValX(5 downto 1);
     ELSIF (OPcode = "111") THEN -----------Lshift OPcode
       IF (CLK'EVENT AND CLK = '1') THEN
            TempValX <= "000" & X;
           Z <= TempValX(4 downto 0) & '0';
       end IF;   
     ELSE
          Null;
     END IF;  
   END IF; END Process; end Circuit;

What's your question? Is the program not working as expected? — Evan M, Dec 03 '18 at 21:13
When i synthesize the program it gives me the error “Else clause after check for clock not supported”. I'm trying to make a schematic to turn in. but the option is grayed out, i'm assuming that it needs to properly run a synthesis in order to make a schematic. — Adrian Gomez, Dec 03 '18 at 22:23
Please read about coding patterns on how to use `rising_edge` or in your case with old-style writing `clk'event` when and how to use. This code is totally broken ... Do not use package `STD_LOGIC_UNSIGNED`. Please indent your code properly, so we can read it. You *use* many `std_logic` related packages, but your code is using type `bit`/`bit_vector` ... — Paebbels, Dec 03 '18 at 23:56
Our lab instructor wants us to use bit_vector over std_logic. Thanks for you input! — Adrian Gomez, Dec 04 '18 at 00:06
Please, if there is anything else that can be improved, let me know! :) I'm happy to increase my knowledge in the subject and the field! — Adrian Gomez, Dec 04 '18 at 00:16
You don't need any of the present use clauses. There's a misplaced `end if;` [that would show up with a structured indentation scheme](https://i.stack.imgur.com/jhkUm.jpg). Also see [\[Synth 8-27\] else clause after check for clock not supported](https://forums.xilinx.com/t5/Welcome-Join/Synth-8-27-else-clause-after-check-for-clock-not-supported/td-p/764098) on the Xilinx Community Forum. There may be other issues with the design specification. — , Dec 04 '18 at 01:30

score 1 · Accepted Answer · answered Dec 04 '18 at 02:29

1

Couple of things stand out.

If you only need to "perform a task at the rising edge of the clock", you only need 'CLK' in your process sensitivity list.
The order of precedence in your if-else inside the process is wrong. All of the opcode decoding logic should be inside the check for rising edge clock.

answered Dec 04 '18 at 02:29

amiller856

36
4

The standard (IEEE Std 1076-2008) contradicts your first point, 10.2 Wait statement. (The 10.2 rules are applicable to the implicit wait statement at the end of a process with a sensitivity list. Notice OPcode is outside the if statement with a clock edge condition.) The second point is contradicted by IEEE Std 1076.6-2004 (RTL Synthesis, withdrawn) 6.1.3 Modeling edge-sensitive storage elements (see async_condition). Also see Example 3. in 6.1.3.1 Edge-sensitive storage from a process with sensitivity list and one clock. The Xilinx error message indicates Xilinx can parse such constructs. – Dec 04 '18 at 02:47

VHDL coding error “Else clause after check for clock not supported”

1 Answers1