Why do I get "Found '0' definitions of operator "+"" when adding bit_vectors? Are Delta Delays a factor?

Question

I'm in the process of coding a 3-bit ALU. The problem I'm running into is in the multiplier, when Opcode = "001". I'm trying to add 3 bit_vectors(5 downto 0), and it's throwing the error "Found '0' definitions of operator "+"". I've looked around and found some links found '0' definitions of operator "+" in VHDL, but adding any packages doesn't seem to fix the error for me.

Also, I read somewhere that since you're coding hardware in VHDL, it's wise to keep in mind delta delays. Since i'm assigning values to a signal in a process, will it actually work to output the final product? Or will the delta delays cause the signals to not be updated until the process is suspended.

The error occurs on line 67, "Z <= t4 + t5 + t6", in the block where Opcode = "001". Thank you to anyone who can give a little advice.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    PORT(
        X,Y   : IN BIT_VECTOR(2 downto 0);
        Opcode : IN BIT_VECTOR(2 downto 0);
        Z      : OUT BIT_VECTOR(5 downto 0);
        CLK   : IN BIT
        );
end ALU;

architecture Behavioral of ALU is
   COMPONENT adder3 is
     PORT (
       A1 ,A2, A3, B1, B2, B3, Cin : IN BIT ;
       Sum1 ,Sum2,  Sum3, Cout : OUT BIT );
    END COMPONENT;

        SIGNAL adder_output: BIT_VECTOR(3 downto 0);
        SIGNAL temp: BIT_VECTOR(2 downto 0);
        SIGNAL t1,t2,t3: BIT_VECTOR(2 downto 0);
        SIGNAL t4,t5,t6: BIT_VECTOR(5 downto 0);
begin

    ADD3: adder3 PORT MAP(
        A1 => X(0),
        B1 => Y(0),
        A2 => X(1),
        B2 => Y(1),
        A3 => X(2),
        B3 => Y(2),
        Cin => '0',
        Sum1 => adder_output(0),
        Sum2 => adder_output(1),
        Sum3 => adder_output(2),
        Cout => adder_output(3)
        );

    PROCESS(X, Y, CLK, Opcode)
        BEGIN
            IF(CLK'EVENT AND CLK='1')THEN
                IF Opcode = "000" THEN
                    Z <= adder_output;
                ELSIF Opcode = "001" THEN
                    IF Y(0) = '1' THEN
                        t1 <= X;
                    ELSE
                        t1 <= "000";
                    END IF;
                    IF Y(1) = '1' THEN
                        t2 <= X;
                    ELSE
                        t2 <= "000";
                    END IF;
                    IF Y(2) = '1' THEN
                        t3 <= X;
                    ELSE
                        t3 <= "000";
                    END IF;
                     t4 <= "000"&t1;
                     t5 <= "00"&t2&"0";
                     t6 <= "0"&t3&"00";
                     Z <= t4+t5+t6;
                ELSIF Opcode = "010" THEN
                    Z <= X AND Y;
                ELSIF Opcode = "011" THEN
                    Z <= X OR Y;
                ELSIF Opcode = "100" THEN
                    Z <= X XOR Y;
                ELSIF Opcode = "101" THEN
                    temp <= NOT X;
                    Z <= "000"&temp;
                ELSIF Opcode = "110" THEN
                    IF Y = "000" THEN
                        Z <= "000"&X(2 downto 0);
                    ELSIF Y = "001" THEN
                        Z <= "00"&X(2 downto 0)&"0";
                    ELSIF Y = "010" THEN
                        Z <= "0"&X(2 downto 0)&"00";
                    ELSIF Y = "011" THEN
                        Z <= X(2 downto 0)&"000";
                    ELSIF Y = "100" THEN
                         Z <= X(1 downto 0)&"0000";
                    ELSIF Y = "101" THEN
                         Z <= X(0)&"00000";
                    ELSE
                         Z <= "000000";
                    END IF;
                ELSE
                    IF Y = "000" THEN
                        Z <= "000"&X(2 downto 0);
                    ELSIF Y = "001" THEN
                        Z <= "0000"&X(2 downto 1);
                    ELSIF Y = "010" THEN
                        Z <= "00000"&X(2);
                    ELSE
                        Z <= "000000";
                    END IF;
                END IF;
           END IF;            
       END PROCESS;
end Behavioral;

Delta delays are not a factor during semantic analysis. There's an explanation of operator overload resolution in the answer to [no function declarations for operator](https://stackoverflow.com/questions/50861761/no-function-declarations-for-operator/50867571#50867571), noting bit_vector and bit are not resolved types. The error reports a failure in overload resolution. Your opcode "000" will encounter a simulator error, there's not a matching element for each element of the assignment target Z (6 elements) and right hand expression (4 elements). (There may be more errors.) — , Dec 01 '18 at 16:18

score 0 · Answer 1 · answered Dec 01 '18 at 14:16

If you want to do unsigned arithmetic with bit_vector, you need to use the numeric_bit_unsigned library that is part of the VHDL 2008 spec. For signed arithmetic, you need to use unsigned or signed types from either numeric_std or numeric_bit (the only difference is the base type).

Why do I get "Found '0' definitions of operator "+"" when adding bit_vectors? Are Delta Delays a factor?

1 Answers1