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Does the VHDL language standard defines the behavior of checking conditions in the if statement in the following situation:

constant one: std_logic: = '1'; -- always '1'
signal vector: std_logic_vector (2 downto 0);

(...)
if (one or vector(3) ) begin

(...)

in such case, should be compilation/elaboration/runtime error (out of range) or if condition should be always true (therefore no need to check value of vector(3)?

J. Doe
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  • It is not C. You will get a compile time out of range error. – Oldfart Oct 26 '18 at 15:18
  • IEEE Std 1076-2008 9.4 Static expressions, 9.4.1 "Certain forms of expression can be evaluated during the analysis of the design unit in which they appear; such an expression is said to be *locally static*." The locally static index constraint (2 downto 0, 9.4.2 Locally static primaries) can be evaluated against the locally static index expression (3). 8.4 Indexed names "...It is an error if an index value does not belong to the range of the corresponding index range of the array." Whether or not non-static expression vector(3) is evaluated (9.2.2 Logical operators "short-circuit operations"). –  Oct 26 '18 at 19:08
  • An if statement has **then** following it's condition and not a **begin** in VHDL. Your snippet doesn't use valid syntax. –  Oct 27 '18 at 18:07

2 Answers2

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You will have an error during the elaboration process. But normally when you write a VHDL code, you don't need the usage of this kind of tricks.

Are you trying to use this code to solve an conception issue ? If for example, you want to use vector(3) only with the vector is larger than 3, so you could use if... generate statement or if ... then statement to do it.

graille
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  • *ghdl -a --std=08 [foo.vhdl](https://www.dropbox.com/s/xiemvvude7kawqj/foo.vhdl?dl=1)* (analysis, -2008) produces `foo.vhdl:13:26:error: static expression violates bounds` for `if one or vector(3) then`, the semantic error defined in IEEE Std 1076-2008 8.4 Indexed names "...It is an error if an index value does not belong to the range of the corresponding index range of the array." The error can be detected at analysis time (the index constraint and index value are both locally static, 9.4 Static expressions). Do you know of a VHDL tool with elaboration and not analysis time detection? –  Oct 27 '18 at 19:17
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And, nand, or and nor operators in VHDL are short-circuit operators in some cases. The behavior depends on the operands types.

You're using type std_logic, which is not listed:

9.2 Operators - General
In general, operands in an expression are evaluated before being associated with operators. For certain operations, however, the right-hand operand is evaluated if and only if the left-hand operand has a certain value. These operations are called short-circuit operations. The binary logical operations and, or, nand, and nor defined for operands of types BIT and BOOLEAN are all short-circuit operations; furthermore, these are the only short-circuit operations.

[...]

NOTE 2—A user-defined operator that has the same designator as a short-circuit operator (i.e., a user-defined operator that overloads the short-circuit operator) is not invoked in a short-circuit manner. Specifically, calls to the user-defined operator always evaluate both arguments prior to the execution of the function.

In case of an or operator, if the first operand is true, the second operand will not be evaluated.
In case of an and operator, if the first operand is false, the second operand will not be evaluated.

I think that std_logic is not listed, is a mistake that was made when incorporating IEEE Std. 1164 into IEEE Std. 1076 for VHDL-2008.

Paebbels
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