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How can it be used from software if it is a hardware semaphore? Is it that there is a software API which is actually implemented in HW?

I ask as I am implementing firmware to interface to some hardware. There is going to be a lot of information exchange between the hardware and the firmware. I overhead talk of hardware semaphore and just wanted to find out more information on it. Some literature on this would be helpful

skaffman
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dubnde
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3 Answers3

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You are mostly correct. There is a SW API that requires some special hardware to work correctly. Implementations of semaphores in software, of which there are a few, are all based on some sort of HW instruction that is guaranteed to be atomic.

Atomicity in HW is required to implement a semaphore. Normally HW instructions are not atomic.

To elaborate somewhat, you need to implement a semaphore by reading and writing a piece of shared memory which is visible to more than 1 processor. Reading and writing that shared piece of memory is not an atomic operation in general: for example if you do a read followed by a write there could be other instructions that are scheduled between the read and write.

Himadri Choudhury
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  • Hi, I think that many times we can avoid HW mutex. for example if processor A only writes to shared memory word from which processor B only reads, there is no need to hw mutex becuase Memory words read/write access is also atomic. What do you think ? – ransh Jun 21 '15 at 06:36
  • @ransh To correctly implement synchronization primitives you need to combine a read and a write in a single atomic block. Single writes or reads will be atomic, but stuff like incrementing and decrementing, which combine a read and a write, normally aren't. – Paul Stelian Feb 02 '19 at 13:17
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The hardware needs to make sure the bus is locked from other masters accessing the resource before the second part of the operation i.e write takes place. Usually this is done at arbitration stage in hardware.

Adil
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In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.

Bharath T S
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