VHDL FSM multi-driven net Q is connected to constant driver, other driver is ignored, what's wrong with my code?

Question

This code is a FSM which is a Moore Machine

Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs of the snail’s brain.

And the code is shown below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity simpfsm is
Port ( A : in STD_LOGIC;
       clk : in STD_LOGIC;
       r   : in STD_LOGIC;
       Y : out STD_LOGIC);
end simpfsm;


architecture Behavioral of simpfsm is
type state_type is (SA,SB,SC);
signal state,next_state:state_type;
begin
SYNC_PROC:process(clk)
begin
if(clk'event and clk='1') then
if(r='1') then
next_state <= SA; -- removed trailing grave accent
else
state <= next_state;
end if;
end if;
end process;

OUTPUT_DECODE:process(state)
begin
case (state) is
when SA =>
Y <= '0';
when SB =>
Y <= '0';
when SC =>
Y <= '1';
when others =>
Y <= '0';
end case;
end process;

NEXT_STATE_DECODE:process(state,A)
begin
next_state <= state;
case (state) is

    when SA =>
        if(A='0') then
            next_state <= SB;
        end if;

    when SB =>
        if(A='1') then
            next_state <= SC;
        end if;

    when SC =>
        if(A='0') then
            next_state <= SB;
        elsif(A='1') then
            next_state <= SA;
        end if;
    when others =>
        next_state <= SA;                       --"if not state then begin with SA"
end case;
end process;
end Behavioral;  -- removed trailing grave accent

The error is [XSIM 43-3249] File D:/Users/93443/project_4/project_4.srcs/sources_1/new/A_11_fsm.vhd, line 22. Unresolved signal "next_state" is multiply driven.

Answer 1

state_type is not a resolved subtype. Multiple drivers are detected during loading prior to model execution after being identified during elaboration.

IEEE Std 1076-2008

14.5 Elaboration of a statement part
14.5.5 Other concurrent statements

All other concurrent statements are either process statements or are statements for which there is an equivalent process statement. Elaboration of a process statement proceeds as follows:

a) The process declarative part is elaborated.
b) The drivers required by the process statement are identified.

6.4.2.3 Signal declarations

... It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal. ...

There are drivers for next_state in processes SYNC_PROC and NEXT_STATE_DECODE

14.7 Execution of a model
14.7.2 Drivers

Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals. There is a single driver for a given scalar signal S in a process statement, provided that there is at least one signal assignment statement in that process statement and that the longest static prefix of the target signal of that signal assignment statement denotes S or denotes a composite signal of which S is a subelement. Each such signal assignment statement is said to be associated with that driver. Execution of a signal assignment statement affects only the associated driver(s).

state_type an enumerated type and is a scalar type:

5.2 Scalar types
5.2.1 General

Scalar types consist of enumeration types, integer types, physical types, and floating-point types. ...

The solution would appear to be to reset state in SYNC_PROC instead of next_state.

If you remove the two extraneous grave accents ('`', 15.2 Character set) your code would be a Minimal, Complete, and Verifiable example despite Tricky's expression of suspicion. I removed them from your code example, after which your code analyzes and elaborates following the change to process SYNC_PROC:

if(r='1') then
state <= SA;  -- WAS next_state

(Note the parentheses around a condition (here r='1') are redundant. In VHDL a condition is known to be an expression with a BOOLEAN value.)

If your simulator allows execution with top level ports it would report the multiple drivers. For those simulators that don't you'd require a testbench instantiating simpfsm:

14.2 Elaboration of a design hierarchy

An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. If an implementation allows these top-level interface objects, it may restrict their allowed forms (that is, whether they are allowed to be interface types, subprograms, packages, or objects), and, in the case of interface objects, their allowed types and modes in an implementation-defined manner.

As you might gather this represents a portability issue for detecting the error without a testbench or depending on an interactive of script driven simulator. The error can demonstrated with ghdl prior to the signal assignment target change:

ghdl -r simpfsm
for signal: .simpfsm(behavioral).next_state
./simpfsm:error: several sources for unresolved signal
./simpfsm:error: error during elaboration

Loading an elaborated design specification into memory is deferred to 'program' execution in compiler based VHDL simulators:

14.2 Elaboration of a design hierarchy

Elaboration of a design hierarchy is completed as follows:

— The drivers identified during elaboration of process statements (see 14.5.5) are created.
— The initial transaction defined by the default value associated with each scalar signal driven by a process statement is inserted into the corresponding driver.

next_state and state both have default values of state_type'LEFT (SA).

6.4.2.3 Signal declarations

In the absence of an explicit default expression, an implicit default value is assumed for a signal of a scalar subtype or for each scalar subelement of a composite signal, each of which is itself a signal of a scalar subtype. The implicit default value for a signal of a scalar subtype T is defined to be that given by T'LEFT.

And this implies detecting multiple drivers occurs during the loading portion of elaboration when each net is identified:

14.7.3.4 Signal update

A net is a collection of drivers, signals (including ports and implicit signals), conversion functions, and resolution functions that, taken together, determine the effective and driving values of every signal on the net.

We see in that part of elaboration (loading here) occurs during execution (ghdl's -r command):

14.2 Elaboration of a design hierarchy

The elaboration of a design hierarchy creates a collection of processes interconnected by nets; this collection of processes and nets can then be executed to simulate the behavior of the design.

Tricky's suspicion is somewhat valid, the grave accents would cause errors during analysis, while the error you provide occurs during elaboration. They can be assumed to be transcription errors here by investigating your reported error first.

Answer 2

Next_stat is driven in the reset of the SYNC_PROC

next_state <= SA;

and also in the NEXT_STATE_DECODE process. You cannot drive it from two processes.

You also have an extra ` for no good reason. Is this the real code?