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Very simple problem with my VHDL code. I have defined the following code:

type irf_array is array(0 to 1) of integer;
signal index : std_logic;
....
index := input(5);
out   := irf_array(index);

When trying to compile this simple code fragement I get the following error:

Error: array index type mismatch [6.4]

So I am wondering if anyone has an idea how I can use the std_logic value as input to my array.

Many thanks!

toolic
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Reini
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  • Out of respect to those who may want to take the time to resolve a problem that you cannot resolve yourself, I would like to suggest to avoid describing it as "very simple" on beforehand. – Jan Decaluwe Mar 11 '11 at 14:46

1 Answers1

4

Your array index needs to be an integer. If you want to use a std_logic based type, you should probably use the signed or unsigned types (which include the concept of a numerical value, unlike a plain std_logic signal) and appropriate type conversion:

type irf_array is array(0 to 1) of integer;
signal index : unsigned(0 downto 0);
....
index(0) := input(5);
out   := irf_array(to_integer(index));

You can use a std_logic_vector instead of the unsigned type, with an extra conversion:

signal index : std_logic_vector(0 downto 0);
...
out   := irf_array(to_integer(unsigned(index)));
Charles Steinkuehler
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    Why not just declare the index as an integer right away? That way you don't have to convert the datatype later on. signal index: integer range 0 to 1; – Philippe Mar 11 '11 at 16:09
  • +1 for using proper 'unsigned' types. But I'd use an integer from the outset – Martin Thompson Mar 14 '11 at 16:26