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I have a quick question, the book I have shows the control values for a store word instruction as such :

Regdst - X
Alusrc 1
Memto-reg X
RegWrite 0
-> MemRead 0
MemWrite 1
Branch 0
ALUOp1 0
ALUOp2 0

The explanation for memto-reg to be "don't care" is because RegWrite is 0 anyway, makes sense. But my question is, why MemRead is 0 ?

As MemRead only puts a value on the ReadData output, and I shouldn't care what value it is for the same reason I shouldn't care what value is after the MemtoReg mux choice, as RegWrite is 0 anyway.

My question is: shouldn't MemRead be don't care instead of 0? And the book made a mistake ? Or am I missing something, because I see in more sources that MemRead is 0 and not don't care in store word(sw) instruction.

FYI: the figure is missing some control datapaths like RegDst Mux but irrelevant to the question I think. Also, same question applies to beq instruction.

enter image description here

TG Person
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    Kudos for making a self contained and clear question! I believe that MemWrite and MemRead must be mutually exclusive. Contrary to registers, in simple architectures memory is usually single ported and the storage technology, say DRAM, usually doesn't allow for a read while a write is being performed. Out of the four possible combinations for MemWrite/Read, 00 means nop, 01 means Read, 10 means Write and 11 is not allowed. Is there anything in the book that could suggest this? – Margaret Bloom Oct 09 '18 at 12:00
  • @MargaretBloom Oh that's it thanks ! I suspected it too but not enough to look specifically for this, it is mentioned in the book that only one of the read/write controls may be asserted on any given clock, because " reading the value of an invalid address can cause problems..." – TG Person Oct 09 '18 at 14:27

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