how to implement makefile shared variable

Question

I need a variable in makefile that can be shared across subdir makefiles ( recursive build strategy), and finally use it for some decision making. I had earlier thought export is the way to do it, but I am not getting desired results.

following are my makefiles:-

Target.mk      (common include for both Makefile.mk & Subdir.mk)
Makefile.mk
Subdir.mk

---

FILE : Target.mk

export TARGET_PROPERTIES :=

---

FILE : Makefile.mk

-include Target.mk

.PHONY : all 
all :
    $(MAKE) -C $(PWD) -f Subdir.mk all
    @echo "#------------------------------------------------------------#"
    @echo "Target build properties"
    @echo $(TARGET_PROPERTIES)
    @echo "#------------------------------------------------------------#"

---

FILE : Subdir.mk

-include Target.mk

TARGET_PROPERTIES+=alpha
TARGET_PROPERTIES+=beta

$(warning $(TARGET_PROPERTIES))

all:
    @echo "Subdir.mk......[OK]"

---

PROBLEM:- I want TARGET_PROPERTIES, to be updated from Subdir.mk and the use the results in Makefile.mk

following is my output

$ make -f Makefile.mk
make -C /cygdrive/c/make_pf -f Subdir.mk all
make[1]: Entering directory `/cygdrive/c/make_pf'
Subdir.mk:8:  alpha beta
Subdir.mk......[OK]
make[1]: Leaving directory `/cygdrive/c/make_pf'
#------------------------------------------------------------#
Target build properties

#------------------------------------------------------------#

in Subdir.mk TARGET_PROPERTIE updates, fine until here.

Subdir.mk:8:  alpha beta

in Makefile.mk after return from "Subdir.mk - all target" it resets to NULL. Not sure what I am doing wrong

P.S. I am using cygwin environment.

Answer 1

Exported environment variables are copied to child processes, so changes there do not propagate back into the parent process.

Your best bet would probably to avoid recursive makefiles and instead include everything from the main Makefile.mk. Google for Recursive Make considered harmful for pointers how to do this.