Default cache parameters, how to change, limitation and more

Question

I am new to rocket chip generator and still learning. First thing I want to know is how to parameterize l1 d cache. I did some research but it seems the info is not up to date. For example, in src/main/scala/config.scala, there is no d cache parameters defined as mentioned in README. Some people mentioned coreplex/config.scala but I couldnt find it either. Will someone please let me know where are the default parameter defined and how to change them? Also, where is the tinycore, bigcore and other predefined core defined?

Answer 1

There are multiple configurations that you can choose while compiling Rocket Chip. You can find these configurations in subsystem/Configs.scala file. By default, make command in vsim and emulator directory uses DefaultConfig parameters.

class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)

class WithNBigCores(n: Int) extends Config((site, here, up) => {
  case RocketTilesKey => {
    val big = RocketTileParams(
    ...
      dcache = Some(DCacheParams(
        rowBits = site(SystemBusKey).beatBits,
        nMSHRs = 1,
        blockBytes = site(CacheBlockBytes))),
      icache = Some(ICacheParams(
        rowBits = site(SystemBusKey).beatBits,
        blockBytes = site(CacheBlockBytes))))
      List.tabulate(n)(i => big.copy(hartId = i))
  }
})

You can find data cache parameters in rocket/HellaCache.scala. Some important parameters defined are:

nSets: Number of cache sets

nWays: Number of cache ways

rowBits: Cache line size