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I found this error in this testbench for SR FF.
While I am compiling it using GHDL in terminal, it is showing the error

; is expected instead of ''

I am just a beginner, so that I can't find the error.
Can anyone please help me?

library ieee;
use ieee.std_logic_1164.all;

entity SR_tb is
end SR_tb;

architecture behavioral of SR_FF is
    component SR_FF is
        port  (S,R,CLOCK:in std_logic;
        Q,QBAR:out std_logic);  
    end component;
signal clock,s,r,q,qbar: std_logic;
constant clock_period : time := 10 ns;
begin
    port_map:SR_FF port map (clock=>CLOCK,s=>S,r=>R,q=>Q,qbar=>QBAR);

clock_process:process
 begin
      clock <='0';
      wait for clock_period/2;
      clock <= '1';
      wait for clock period/2;
end process;
stim_proc:process
begin 
       s<= '0';
        r<= '0';
        wait for 50 ns;   
        s<= '0';
        r<= '1';
        wait for 50 ns;
        s<= '1';
        r<= '0';
        wait for 50 ns;
        s<= '1';
        r<= '1';
        wait for 50 ns;
assert false report "reached end of test";
wait;
end process;

end behavioral;

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