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Does anyone have a pointer to measurements of how fast a behavioral model written in SystemC is compared to the same model written in SystemVerilog? Or at least first hand experience of the relative simulation speed of the two, when modeling the same thing?

To clarify, this is for high level system simulation, where the model is the minimum code to mimic the behavior. It's decidedly not synthesizable. In System Verilog, it would use as many non-synthesizable behavioral constructs as possible, for maximum execution speed. The point is, we're asking about an apples to apples comparison that someone did, where they tried to do both: stay high level (non-synthesizable), and make the code as close to equivalent as possible between the two languages.

It would be great if they stated the SystemVerilog environment used, and what machine each was run on, in order to be able to translate. Hopefully can be useful to a variety of people in choosing approach.

Thanks!

seanhalle
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  • system verilog by itself consists of several parts: rtl, gates, test bench, constraint solver, coverage. Which parts are you interested in? Also verilog has a set of semantics which is different from a convenient c++ language. What kind of semantic mapping you have in mind? – Serge Aug 01 '18 at 15:14

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Like with other language benchmarks it is not possible to answer in general, because it depends on multiple factors like modeling style, compiler vendor and version, compilation options.

Also there are tools to convert Verilog to C++ and C++ to Verilog. So you can always match simulation performance by converting from one language to other.

Verilog can be converted to C++/SystemC using Verilator https://www.veripool.org/wiki/verilator

To convert C++/SystemC into Verilog you can use HLS (High-level synthesis) toos.

random
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  • none of the conversion tools you mentioned completely work for system verilog in particular for test bench. – Serge Aug 01 '18 at 15:10
  • @Serge OP mentioned "same behavioral model". I've assumed he meant RTL behavioral model. Yes, converters do not work for TLM-2.0 models. – random Aug 01 '18 at 15:16
  • Thanks for the comment, but our experience has been that after conversion, Verilog code converted into C++ by Verilator runs on the order of 100x to 1000x slower than a behavioral model. Behavioral models are not synthesizable, but just the minimum code to mimic the behavior. Plus, too, Verilator doesn't support System Verilog's behavioral constructs, which are not synthesizable. I've edited to question to clarify. – seanhalle Aug 04 '18 at 23:15