how write an 8 bit up counter in vhdl with dataflow (structural) coding?

Question

I am trying write a 8 bit up counter from 0 to 99 then return to 0 , with jk flip flop in VHDL, with active hdl program. but its do nothing. where is the problem?

jk flip flop with asynchron reset :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity JK is
port(
    J, K, clk, clr : in  std_logic;
    Q, Qbar     : out std_logic
);
end JK;

architecture arch of JK is
signal D : std_logic;
signal Dn : std_logic;
signal clkn : std_logic;
signal clrn : std_logic;
signal o1 : std_logic := '1';
signal o2 : std_logic := '0';
signal o3 : std_logic := '0';
signal o4 : std_logic := '1';
signal o5 : std_logic := '0';
signal o6 : std_logic := '1';
signal o7 : std_logic := '1';
signal o8 : std_logic := '0';


begin

D <= (o8 and (not K)) or (o7 and J);
Dn <= not D;
clkn <= not clk;
clrn <= not clr;
o1 <= Dn and clkn;
o2 <= D  and clkn and clrn;
o3 <= not (o4 or o1 or clr);
o4 <= o3 nor o2;
o5 <= o3 and clk;
o6 <= o4 and clk;
o7 <= o8 nor o5;
o8 <= o7 nor o6;
Qbar <= o7;
Q    <= o8;
end arch;

8 bit up counter code :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity counter_8bit is
port(
    clk :in std_logic;
    output : out std_logic
);
end counter_8bit;

architecture arch of counter_8bit is
signal toninty : std_logic := '0';
signal Qout : std_logic_vector(7 downto 0) := "00000000";   
component jk
port(
    J : in STD_LOGIC;
    K : in STD_LOGIC;
    clk : in STD_LOGIC;
    clr : in STD_LOGIC;
    Q : out STD_LOGIC;
    Qbar : out STD_LOGIC);
end component;
for all: jk use entity work.jk(arch);

signal j1,j2,j3,j4,j5,j6,j7,j8,k1,k2,k3,k4,k5,k6,k7,k8:std_logic := '0';          
signal Qbar : std_logic;
signal clock : std_logic;
begin
toninty <= Qout(0) and Qout(1) and (not Qout(2)) and (not Qout(3)) and (not Qout(4)) and Qout(5) and Qout(6) and (not Qout(7));
clock <= not(clk);
j1 <= '1';
j2 <= Qout(0) after 1 ps;
j3 <= Qout(0) and Qout(1);
j4 <= j3 and Qout(2);
j5 <= j4 and Qout(3);
j6 <= j5 and Qout(4);
j7 <= j6 and Qout(5);
j8 <= j7 and Qout(6);

k1 <= '1';
k2 <= Qout(0) after 1 ps;
k3 <= (Qout(0) and Qout(1));
k4 <= (j3 and Qout(2));
k5 <= (j4 and Qout(3));
k6 <= (j5 and Qout(4));
k7 <= (j6 and Qout(5));
k8 <= (j7 and Qout(6));

a1 : jk
port map(
    J => j1,
    K => k1,
    clk => clock,
    Q => Qout(0),
    Qbar => Qbar,
    clr => toninty
);
a2 : jk
port map(
    J => j2,
    K => k2,
    clk => clock,
    Q => Qout(1),
    Qbar => Qbar,
    clr => toninty
);
.
.
.
.
a8 : jk
port map(
    J => j8,
    K => k8,
    clk => clock,
    Q => Qout(7),
    Qbar => Qbar,
    clr => toninty
);

output <= Qout;

end arch;

output example :

0 1 2 3 4 ... 99 0 1 2 ... 99 0 1 2 3 ...

I searched alot but didn't find a solution.it's compiled without any errors but I got UU in output and can't find the problem.