Functions in Makefile

Question

I am writing a Makefile with a lot of repetitive stuff, e.g.

debug_ifort_Linux:
        if [ $(UNAME) = Linux ]; then                           \
          $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..."  \
                  TARGET=$@ LEXT="ifort_$(UNAME)" -e syst;      \
        else                                                    \
          echo $(err_arch);                                     \
          exit 1;                                               \
        fi

where the target 'syst' is defined, the variable 'UNAME' is defined (and is usually Linux, but might also by Cygwin or OSF1) and the variables 'difort' and 'err_arch' are also defined. This block of code is used very many times for different compiler targets (using a name convention of ''). Since this is a huge amount of redundant code, I would like to be able to write it in a more simple manner. E.g., I would like to do something like this:

debug_ifort_Linux:
        compile(uname,compiler,flags,petsc_flags,target,lext)

where compile could be a function doing the code above based on the arguments. Does anyone have any idea how I could accomplish this?

score 40 · Accepted Answer · edited Mar 31 '21 at 10:26

40

There are 3 related concepts:

The refactored result could look like this:

ifeq ($(UNAME),Linux)
    compile = $(MAKE) FC=$(1) FFLAGS=$(2) PETSC_FFLAGS=$(3) \
                      TARGET=$@ LEXT="$(1)_$(UNAME)" -e syst
else
    define compile =
        echo $(err_arch)
        exit 1
    endef
endif
        

debug_ifort:
        $(call compile,ifort,$(difort),"...")

That one \ that is left is to continue the $(MAKE) line for the shell. No multi-line variable is necessary here, because it is just one line of shell code. Multi-line variables are only used in the else block.

If you don't need parameters you can use := assignment and just expand the method with $(compile) (see canned recipes)

Note: Using make prior to version 3.82, the = was not recognized at the end of the define statement for me. I fixed this by using define compile instead.

edited Mar 31 '21 at 10:26

Zoe

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answered Dec 22 '12 at 02:17

JonnyJD

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Why is this better than the previous reply that is currently marked as correct? – Karl Yngve Lervåg Dec 23 '12 at 10:20
1

You should use multi-line variables, rather than \. Which again would be "too much to just edit that answer" (as far as I received reviews so far) – JonnyJD Dec 23 '12 at 10:23
And explaining multiline variables is a bit too much for a comment. But you don't have to agree, of course. – JonnyJD Dec 23 '12 at 10:29
I realize that this is exactly what I ended up doing in the end. Thanks for noticing and adding an improved answer. :) – Karl Yngve Lervåg Dec 25 '12 at 12:13

ephemient · Answer 2 · 2009-02-04T23:12:26.727

40

You're looking for the call function.

compile =                                                 \
        if [ $(UNAME) = $(1) ]; then                      \
          $(MAKE) FC=$(2) FFLAGS=$(3) PETSC_FFLAGS="..."  \
                  TARGET=$@ LEXT="$(4)_$(UNAME)" -e syst; \
        else                                              \
          echo $(err_arch);                               \
          exit 1;                                         \
        fi

debug_ifort_Linux:
        $(call compile,Linux,ifort,$(difort),ifort)

If you can restructure your Makefile a bit, though, you should see if you can use make's conditionals instead of sh's.

edited Feb 04 '09 at 23:12

answered Feb 03 '09 at 15:59

ephemient

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Thanks, this worked! :) I do not see directly how I can use make's conditionals to do the same as what I want. At least not without a _lot_ of restructuring. Of course, this might just be because I'm not very experienced with writing Makefiles... – Karl Yngve Lervåg Feb 03 '09 at 16:10
This is a prime example where you should use [multi-line variables](http://www.gnu.org/software/make/manual/html_node/Multi_002dLine.html). – JonnyJD Dec 23 '12 at 15:21

Functions in Makefile

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