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I've got two 115bits unsigned vectors. I have to do some mod calculations on them, but Quartus shows those errors.

Error: In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Error: In lpm_divide megafunction, LPM_WIDTHD must be less than or equal to 64
Error: Can't elaborate inferred hierarchy "lpm_divide:Mod0"

I fully understand, that numbers are too large to perform mod. Is there a way/library/any idea how to solve this problem? I would love to avoid using any "substracting loop", and be as simple as possible. VHDL is not my world, and after academic project I will abandon it with pleasure :P

Application has to calculate modulo inversion. As far as I am not master from VHDL, I've tried doing it using fast powering + mod alghoritm. Application can sucks, it just has to work :d

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.altera_primitives_components.all;

entity inwersja is
    port(
        a: in unsigned(114 downto 0);
        clk: in std_logic;
        start: in std_logic;
        reset: in std_logic;
        c: out unsigned(114 downto 0);
        ready: out std_logic);
    end inwersja;


architecture i1 of inwersja is
    begin
    process(clk)
        variable tempOutput : unsigned(114 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
        variable temp : unsigned (114 downto 0):= a;
        variable modul: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101011";
        variable power: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001";
        variable counter: integer := 0;
        begin
            if reset='1' then
                tempOutput := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
                ready <= '0';
            elsif clk'event and clk='1' then
                if start='0' then
                    ready<='0';
                else
                    if (counter < 115) then
                        if (power(counter) /= '0') then
                            tempOutput := (tempOutput * temp) mod modul;
                        end if;
                        temp := (temp * temp) mod modul;

                        counter := counter + 1;
                    elsif (counter = 115) then
                        ready <= '1';
                    end if;
                end if;
            end if;
            c <= tempOutput;
    end process;
end i1;
pawel-witkowski
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  • Is this RTL code? If so nobody can help you. as synthesis of div/mod is not supported by any tool I know (other then by powers of two that is) – Oldfart Jun 01 '18 at 05:40
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    @Paebbels pasted code in Question. – pawel-witkowski Jun 01 '18 at 08:35
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    Unless you have a very low clock frequency and a lot of logic, you are not going to realize this algorithm in one clock cycle. An FPGA is not a magic box that automatically speed up your algorithm. You need to start thinking in hardware: what components do you need to realize your function... – JHBonarius Jun 01 '18 at 09:46
  • As I said the 'mod' operation can not be synthesized. Even if you work around the 64-bit problem, your code will simulate but not execute on hardware. – Oldfart Jun 01 '18 at 10:47
  • Simulation is enough, I'm not going to upload it on any device – pawel-witkowski Jun 01 '18 at 12:11
  • I tried your code using Vivado and Verilog. No error messages! No results either because temp starts at 0 so all results become zero. – Oldfart Jun 01 '18 at 13:42
  • Sry, I was focused on the 64bit modulo problem, and didnt notice that I've misplaced order of operations. – pawel-witkowski Jun 01 '18 at 20:37
  • You say you only want simulation, but the errors you show are related to synthesis. – JHBonarius Jun 02 '18 at 05:51
  • This should compile (without the unnecessary and non-standard lib/use clauses. What it does is another matter; supply a testbench with a testcase and expected outputs if you still need help. –  Jun 02 '18 at 11:01

0 Answers0