Modelsim Failed to open VHDL file "memfile.dat" in rb mode

Question

I have a memory VHDL code that opens a .dat file to access some assembly instructions .... This how I did it:

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all; 
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_TEXTIO.all;

entity memory is 
generic(width: integer);
port(clk, memwrite   : in  STD_LOGIC;
     addr            : in  STD_LOGIC_VECTOR(width-1 downto 0);
     writedata       : in  STD_LOGIC_VECTOR(width-1 downto 0);
     memdata         : out STD_LOGIC_VECTOR(width-1 downto 0);
     byte_ena        : in  STD_LOGIC_VECTOR(3 downto 0));
end;

architecture behave of memory is
begin
begin
process is
    file mem_file: text open read_mode is "C:\Users\anoir\Documents\Lab_exercise\lab3\work\memfile.dat";
    variable L: line;
    variable ch: character;
    variable index : integer;
    variable result : std_logic_vector(31 downto 0);
    type ramtype is array (511 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
    variable mem: ramtype;
begin
    -- initialize memory content with data from file
    -- only the first eight characters (one byte = eight bit each) are read from each line
    -- thus any character after these is interpreted as comment 
    for i in 0 to 511 loop -- clear all contents first
        mem(conv_integer(i)) := X"00000000";
    end loop;
    index := 0; 
    while not endfile(mem_file) loop
        readline(mem_file, L);
    hread(L,result);
        mem(index) := result;
        index := index + 1;
    end loop;
    -- read or write memory
    loop
        if (clk'event and clk = '1') then
            if (memwrite = '1') then
              -- byte selection
              if (byte_ena = "0001") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"ffffff00") or writedata);
              elsif (byte_ena = "0010") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"ffff00ff") or writedata);
              elsif (byte_ena = "0100") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"ff00ffff") or writedata);
              elsif (byte_ena = "1000") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"00ffffff") or writedata);
              elsif (byte_ena = "0011") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"ffff0000") or writedata);
              elsif (byte_ena = "1100") then
                mem(conv_integer(addr(10 downto 2))) := ((mem(conv_integer(addr(10 downto 2))) and X"0000ffff") or writedata);
              else
                mem(conv_integer(addr(10 downto 2))) := writedata;
              end if;
            end if;
        end if;
        memdata <= mem(conv_integer(addr(10 downto 2)));
        wait on clk, addr;
    end loop;
end process;
end;

This is what the memfile.dat contains:

8c010020 lw $1, 0x20($0)
8c020024 lw $2, 0x24($0)
00221820 add $3, $1, $2
ac030028 sw $3, 0x28($0)
08000000 j 0

I get this error

Fatal: (vsim-7) Failed to open VHDL file "memfile.dat" in rb mode.
# No such file or directory. (errno = ENOENT)

I have read this answer but i did not get it i dont have work under the Modelsim installation folder. The only one I got is in the project directory. How can i fix this?

PS I am using modelsim student edition 10.4a with Win 10